SNVSCD1 September   2024 LM706A0-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN)
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)
      3. 6.3.3  Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On-Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Shunt Current Sensing
      13. 6.3.13 Hiccup Mode Current Limiting
      14. 6.3.14 Device Configuration (CONFIG)
      15. 6.3.15 Single-Output Dual-Phase Operation
      16. 6.3.16 Pulse Frequency Modulation (PFM) / Synchronization
      17. 6.3.17 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Active Mode
      4. 6.4.4 Sleep Mode
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
      3. 7.1.3 Maximum Ambient Temperature
        1. 7.1.3.1 Derating Curves
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency, Wide Input, 400kHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 7.2.1.2.3 Buck Inductor
          4. 7.2.1.2.4 Current-Sense Resistance
          5. 7.2.1.2.5 Output Capacitors
          6. 7.2.1.2.6 Input Capacitors
          7. 7.2.1.2.7 Frequency Set Resistor
          8. 7.2.1.2.8 Feedback Resistors
          9. 7.2.1.2.9 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High Efficiency 24V to 3.3V 400kHz Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Design and Layout
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Compensation Components

Choose compensation components for a stable control loop using the procedure outlined as follows.

  1. Based on a specified loop gain crossover frequency, fC, of 40kHz, use Equation 42 to calculate RCOMP, assuming an effective output capacitance of 82µF. Choose a standard value for RCOMP of 5.36kΩ.
    Equation 42. R C O M P = 2 × π × f C × V O U T V R E F × R S × G C S g m × C O U T = 2 × π × 40 k H z × 5 V 0.8 V × 5 m Ω × 10 1200 µ S × 82 µ F = 5.37 k Ω  
  2. To provide adequate phase boost at crossover while also allowing a fast settling time during a load or line transient, select CCOMP to place a zero at the higher of (1) one tenth of the crossover frequency, or (2) the load pole. Choose a standard value for CCOMP of 6.8nF.
    Equation 43. C C O M P = 10 2 × π × f C × R C O M P = 10 2 × π × 40 k H z × 5.36 k Ω = 7.42 n F

    Such a low capacitance value also helps to avoid output voltage overshoot when recovering from dropout (when the input voltage is less than the output voltage setpoint and VCOMP is railed high).

  3. Calculate CHF to create a pole at the ESR zero and to attenuate high-frequency noise at COMP. CBW is the bandwidth-limiting capacitance of the error amplifier. Select a standard value for CHF of 47pF.
    Equation 44. C H F = 1 2 × π × f E S R × R C O M P - C B W = 1 2 × π × 500 k H z × 5.36 k Ω - 38 p F = 21 p F
Note:

Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from operation in dropout.