SNOSDB8A June   2021  – December 2021 LM74701-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage
      2. 8.3.2 Charge Pump
      3. 8.3.3 Gate Driver
      4. 8.3.4 Enable
      5. 8.3.5 Battery Voltage Monitoring (SW)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Conduction Mode
        1. 8.4.2.1 Regulated Conduction Mode
        2. 8.4.2.2 Full Conduction Mode
        3. 8.4.2.3 VDS Clamp Mode
      3. 8.4.3 Reverse Current Protection Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Considerations
        2. 9.2.2.2 MOSFET Selection
        3. 9.2.2.3 Charge Pump VCAP (CVCAP) and Input Capacitance (CIN)
        4. 9.2.2.4 Output Capacitance (COUT)
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
    4. 9.4 OR-ing Application Configuration
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3 Application Curves

GUID-959E6EEB-493E-42EF-AAEF-79183DC13C3D-low.pngFigure 9-4 ISO 7637-2 Pulse 1
GUID-20210915-SS0I-CXKJ-3KKK-R5TWLRSS5VM7-low.png
Time (100 µs/DIV)
Figure 9-6 Response to ISO 7637-2 Pulse 2A (+112 V)
GUID-20210915-SS0I-88VR-VVTS-LTCQTXZW5BDT-low.png
Time (20 ms/DIV)
Figure 9-8 Response to ISO 16750 Pulse 5B (35-V Suppressed Load Dump)
GUID-20210915-SS0I-L5VX-GPF8-PKGTDGN3LCM6-low.png
Time (10 ms/DIV)
Figure 9-10 Startup With 3-A Load
GUID-20210915-SS0I-SHP6-7ZML-JRLBXVRZSMFZ-low.png
Time (1 ms/DIV)
Figure 9-5 Response to ISO 7637-2 Pulse 1 (–100 V)
GUID-20210915-SS0I-BGRS-GDCG-MLTHXCTLBP90-low.png
Time (200 ms/DIV)
Figure 9-7 Response to ISO 7637-2 Pulse 2B
GUID-20210915-SS0I-RHSV-Z4NK-SMSGPW1P9GM1-low.png
Time (40 µs/DIV)
Figure 9-9 Response to LV124 E-10 (Input Micro Short, 100 μs)
GUID-20210915-SS0I-SRWG-9ZXV-6ZT4GXDMLQ1N-low.png
Time (10 ms/DIV)
Figure 9-11 Startup With 6-A Load