SNOSDC2B September   2021  – July 2022 LM74721-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reverse Battery Protection (A, C, GATE)
        1. 8.3.1.1 Input TVS Less Operation: VDS Clamp
      2. 8.3.2 Load Disconnect Switch Control (PD)
      3. 8.3.3 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
      4. 8.3.4 Boost Regulator
    4. 8.4 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Boost Converter Components (C2, C3, L1)
        2. 9.2.2.2 Input and Output Capacitance
        3. 9.2.2.3 Hold-Up Capacitance
        4. 9.2.2.4 MOSFET Selection: Q1
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Load Disconnect Switch Control (PD)

The PD pin provides a 50-µA drive and 88-mA peak pulldown strength for the load disconnect switch stage. Connect the Gate of the FET to PD pin. Place a 18-V Zener (Dz) across the FET gate and source.

For inrush current limiting, connect CdVdT capacitor and R1 as shown in Figure 8-3.

Figure 8-3 Inrush Current Limiting

The CdVdT capacitor is required for slowing down the PD voltage ramp during power up for inrush current limiting. Use Equation 1 to calculate CdVdT capacitance value.

Equation 1.

where IPD_DRV is 50 μA (typical), IINRUSH is the inrush current, and COUT is the output load capacitance. An extra resistor, R1, in series with the CdVdT capacitor improves the turn-off time.

PD is pulled low during the following conditions:

  • During an OV event with the OV pin voltage rising above the V(OVR) threshold

  • When the EN pin is pulled low with V(EN) driven lower than V(EN_IL) level

  • When the voltage at VS pin drops below the V(VS POR) falling threshold

During these conditions, the FET Q1 turns OFF with its GATE connected to its SOURCE terminal through the external Zener (Dz).

Use Equation 2 to calculate the peak power dissipated in the LM74721-Q1 at the instance of PD pulldown.

Equation 2.

where

  • IPDSINK_peak is the peak sink current of 88 mA (typical)

In the system designs with input voltage above 48 V, TI recommends to place a resistor, RPD, in series with the PD pin as shown in Figure 8-3. The peak power dissipation during the pulldown events gets distributed in RPD and the internal PD switch. A resistor value in the range of 270 Ω to 330 Ω can be selected to limit the device power dissipation within the safe limits.