SNOSDC2B September   2021  – July 2022 LM74721-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reverse Battery Protection (A, C, GATE)
        1. 8.3.1.1 Input TVS Less Operation: VDS Clamp
      2. 8.3.2 Load Disconnect Switch Control (PD)
      3. 8.3.3 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
      4. 8.3.4 Boost Regulator
    4. 8.4 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Boost Converter Components (C2, C3, L1)
        2. 9.2.2.2 Input and Output Capacitance
        3. 9.2.2.3 Hold-Up Capacitance
        4. 9.2.2.4 MOSFET Selection: Q1
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VA_POR(DLY) A (low to high) to GATE Turn-On delay V(A) ↑ V(A_POR)  to V(GATE-A) > 5V, C(GATE-A) = 10 nF 200 µs
tReverse delay Reverse voltage detection to Gate Turn-Off delay V(A) – V(C) = +30 mV to –100 mV, V(GATE-A) <1V, C(GATE-A) = 10 nF 0.47 0.81
tForward recovery Forward voltage detection to Gate Turn-On delay V(A) – V(C) = –100 mV to 700 mV, V(GATE-A) >5V, C(GATE-A) = 10 nF 1.9 2.9
tEN_OFF(DLY)PD EN to PD Delay EN ↓ to PD ↓ 6.5 12
tOV_OFF(DLY)PD OV to PD Deglitch OV ↑ to PD ↓ 0.9 1.5
tPD_Pk Peak Pulldown duration I(PD_SINK,Pk)   ↑ to     I(PD_SINK,DC) ↓ 11 38 65