SNOSDD9 December   2022 LM7481

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump
      2. 8.3.2 Dual Gate Control (DGATE, HGATE)
        1. 8.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 8.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 8.3.3 Overvoltage Protection and Battery Voltage sensing (VSNS, SW, OV)
      4. 8.3.4 Low Iq Shutdown and Undervoltage Lockout (EN/UVLO)
    4. 8.4 Device Functional Modes
    5. 8.5 Application Examples
      1. 8.5.1 Redundant Supply OR-ing With Inrush Current Limiting, Overvoltage Protection and ON/OFF Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Automotive Reverse Battery Protection
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Design Considerations
        2. 9.2.3.2 Charge Pump Capacitance VCAP
        3. 9.2.3.3 Input and Output Capacitance
        4. 9.2.3.4 Hold-up Capacitance
        5. 9.2.3.5 Overvoltage Protection and Battery Monitor
      4. 9.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 9.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 9.2.6 TVS selection
      7. 9.2.7 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 TVS Selection for 12-V Battery Systems
      3. 9.4.3 TVS Selection for 24-V Battery Systems
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Redundant Supply OR-ing With Inrush Current Limiting, Overvoltage Protection and ON/OFF Control

Figure 8-5 Redundant Supply OR-ing With Overvoltage Protection and ON/OFF Control

Figure 8-5 shows the implementation of dual OR-ing with inrush current limiting, overvoltage protection and power path ON/OFF control. The input side SMBJ36CA TVS across the ideal diodes is required for ISO7637 Pulse 1 transient suppression to limit the input voltage within the device max voltage rating of –65 V.

R1 and R2 are the programming resistors for overvoltage protection (OVP) threshold. When the voltage at OVP pin exceeds OVP cut-off reference threshold then the HGATE driver turns OFF the FET Q3, disconnecting the power path and protecting the downstream load. HGATE goes high once the OVP pin voltage goes below the OVP falling hysteresis threshold. Use 0.1-μF to 1-μF capacitor across VS to CAP pins of the LM74810. This is the charge pump capacitor and acts as the supply for both the DGATE and HGATE driver stages. The DGATE driver of the LM74810 is equipped with 60-mA peak source current and 1.5-A peak sink current capability resulting in fast and efficient transient responses during the ISO16750 or LV124 short interruptions as well as AC superimpose testing.

Pull EN low during the sleep/standby mode. With EN low, both the DGATE and HGATE drivers are pulled low turning OFF both the power FETs. VOUT1 gets disconnected from the VBATT rail reducing the system IQ. VOUT2 is gets power through the body diode of the MOSFET Q2 and this supply can be utilized for always ON loads. The LM74810 draws a 2.87-μA current during this mode.