SNOSDE6B december   2022  – july 2023 LM74900-Q1 , LM74910-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. Parameter Measurement Information
  10. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump
      2. 9.3.2 Dual Gate Control (DGATE, HGATE)
        1. 9.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 9.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 9.3.3 Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
        1. 9.3.3.1 Pulse Overload Protection, Circuit Breaker
        2. 9.3.3.2 Overcurrent Protection With Latch-Off
        3. 9.3.3.3 Short Circuit Protection (ISCP)
        4. 9.3.3.4 Analog Current Monitor Output (IMON)
      4. 9.3.4 Undervoltage Protection, Overvoltage Protection, and Battery Voltage Sensing (UVLO, OV, SW)
      5. 9.3.5 Low IQ SLEEP Mode (SLEEP)
      6. 9.3.6 Ultra Low IQ Shutdown (EN)
  11. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical 12-V Reverse Battery Protection Application
      1. 10.2.1 Design Requirements for 12-V Battery Protection
      2. 10.2.2 Automotive Reverse Battery Protection
        1. 10.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 10.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 10.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 Design Considerations
        2. 10.2.3.2 Charge Pump Capacitance VCAP
        3. 10.2.3.3 Input and Output Capacitance
        4. 10.2.3.4 Hold-Up Capacitance
        5. 10.2.3.5 Selection of Current Sense Resistor, RSNS
        6. 10.2.3.6 Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP)
        7. 10.2.3.7 Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON) Selection
        8. 10.2.3.8 Overvoltage Protection and Battery Monitor
      4. 10.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 10.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 10.2.6 TVS Selection
      7. 10.2.7 Application Curves
    3. 10.3 Addressing Automotive Input Reverse Battery Protection Topologies With LM749x0-Q1
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Transient Protection
      2. 10.4.2 TVS Selection for 12-V Battery Systems
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application Information

LM749x0-Q1 controls two N-channel power MOSFETs with DGATE used to control diode MOSFET to emulate an ideal diode and HGATE controlling second MOSFET for power path cut-off when disabled or during an overcurrent, overvoltage, undervoltage events. HGATE controlled MOSFET can be used to clamp the output during overvoltage or load dump conditions. LM749x0-Q1 can be placed into low quiescent current mode using EN or SLEEP, where both DGATE and HGATE are turned OFF.

The device has a separate supply input pin (VS). The charge pump is derived from this supply input. With the separate supply input provision and separate GATE control architecture, the LM749x0-Q1 device drives back to back connected MOSFET in common drain topology thus enabling various system architectures such as power supply ORing and Power supply priority MUX applications. With these various topologies, the system designers can design the front-end power system to meet various system design requirements.