SNOSDE6B december   2022  – july 2023 LM74900-Q1 , LM74910-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump
      2. 9.3.2 Dual Gate Control (DGATE, HGATE)
        1. 9.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 9.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 9.3.3 Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
        1. 9.3.3.1 Pulse Overload Protection, Circuit Breaker
        2. 9.3.3.2 Overcurrent Protection With Latch-Off
        3. 9.3.3.3 Short Circuit Protection (ISCP)
        4. 9.3.3.4 Analog Current Monitor Output (IMON)
      4. 9.3.4 Undervoltage Protection, Overvoltage Protection, and Battery Voltage Sensing (UVLO, OV, SW)
      5. 9.3.5 Low IQ SLEEP Mode (SLEEP)
      6. 9.3.6 Ultra Low IQ Shutdown (EN)
  11. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical 12-V Reverse Battery Protection Application
      1. 10.2.1 Design Requirements for 12-V Battery Protection
      2. 10.2.2 Automotive Reverse Battery Protection
        1. 10.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 10.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 10.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 Design Considerations
        2. 10.2.3.2 Charge Pump Capacitance VCAP
        3. 10.2.3.3 Input and Output Capacitance
        4. 10.2.3.4 Hold-Up Capacitance
        5. 10.2.3.5 Selection of Current Sense Resistor, RSNS
        6. 10.2.3.6 Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP)
        7. 10.2.3.7 Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON) Selection
        8. 10.2.3.8 Overvoltage Protection and Battery Monitor
      4. 10.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 10.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 10.2.6 TVS Selection
      7. 10.2.7 Application Curves
    3. 10.3 Addressing Automotive Input Reverse Battery Protection Topologies With LM749x0-Q1
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Transient Protection
      2. 10.4.2 TVS Selection for 12-V Battery Systems
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) =  V(OUT) = V(VS) = 12 V, C(CAP) = 0.1 µF, V(EN) , V(SLEEP)= 2 V,  over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
V(VS) Operating input voltage 3 65 V
V(VS_PORR) VS POR threshold, rising 2.4 2.6 2.9 V
V(VS_PORF) VS POR threshold, falling 2.2 2.4 2.7 V
I(SHDN) SHDN current, I(GND) V(EN) = 0 V 2.5 5 µA
I(SLEEP) SLEEP mode current, I(GND) V(EN) = 2 V, V(SLEEP) = 0 V 5.5 10 µA
I(Q) Total System Quiescent current, I(GND) V(EN) = 2 V 630 750 µA
V(A) =  V(VS) = 24 V, V(EN) = 2 V 635 750 µA
I(REV) I(A)  leakage current during Reverse Polarity, 0 V ≤ V(A) ≤ – 65 V –100 –35 µA
I(OUT) leakage current during Reverse Polarity –1 –0.3 µA
ENABLE
V(ENF) Enable rising threshold voltage  0.6 0.8 1.05 V
V(ENF) Enable threshold voltage for low Iq shutdown, falling 0.41 0.7 0.98 V
I(EN) 0 V ≤ V(EN) ≤  65 V 55 200 nA
UNDER VOLTAGE LOCKOUT COMPARATOR (SW, UVLO)
V(UVLOR) UVLO threshold voltage, rising 0.585 0.6 0.63 V
V(UVLOF) UVLO threshold voltage, falling 0.533 0.55 0.573 V
I(UVLO) 0 V ≤ V(UVLO) ≤  5 V 50 200 nA
OVER VOLTAGE PROTECTION AND BATTERY SENSING (SW, OV) INPUT
R(SW) Battery sensing disconnect switch resistance 3 V ≤ V(A) ≤ 65 V 10 22.5 46 Ω
V(OVR) Overvoltage threshold input, rising 0.585 0.6 0.63 V
V(OVF) Overvoltage threshold input, falling 0.533 0.55 0.573 V
I(OV) OV Input leakage current 0 V ≤ V(OV) ≤ 5 V 50 200 nA
CURRENT SENSE AMPLIFIER
V(OFFSET) Input referred offset (VSNS to VIMON scaling) RSET = 50Ω, RIMON =  5kΩ, 10kΩ (corresponds to  VSNS = 6mV to 30mV) Gain of 45 and 90 respectively. -2.1 2.1 mV
V(GE_SET) VSNS to VIMON scaling RSET = 50Ω, RIMON =  5kΩ, (corresponds to  VSNS = 6mV to 30mV)  82 90 97
V(SNS_TH) OCP comparator threshold, rising (ILIM) 1.08 1.22 1.32
V(SNS_TH) OCP comparator threshold, falling (ILIM) 1.02 1.15 1.25 V
ISCP SCP Input Bias current VISCP = 12V 9.5 10.5 12 µA
V(SNS_SCP) SCP threshold R(ISCP) = 0Ω (ISCP connected to VS) 17.86 20 22.77 mV
V(SNS_SCP) SCP threshold R(ISCP) = 1kΩ (external) 31 mV
IMON_ACC Current monitor output accuracy VSENSE = 20mV -12.5 12.5 %
FAULT
R(FLT) FLT_I Pull-down resistance 11 25 60 Ω
I_FLT FLT Input leakage current 0 V ≤ V(FLT) ≤ 20 V –100 400 nA
DELAY TIMER (TMR)
I(TMR_SRC_CB) TMR source current 65 85 97 µA
I(TMR_SRC_FLT) TMR source current  1.94 2.7 3.4 µA
I(TMR_SNK) TMR sink  current 2 2.7 3.15 µA
V(TMR_OC) Voltage at TMR pin for IWRN shut off 1.1 1.2 1.4 V
V(TMR_FLT) Voltage at TMR pin for IFLT triggerring 1.04 1.1 1.2 V
V(TMR_LOW) Voltage at TMR pin for AR counter falling threshold 0.1 0.2 0.3 V
N(A_R_Count) Number of autoretry cycles 32
CHARGE PUMP (CAP)
I(CAP) Charge Pump source current (Charge pump on) V(CAP) – V(A) = 7 V, 6 V ≤ V(S) ≤ 65 V 1.3 2.7 mA
V(CAP) – V(A) = 7 V, VS= 65 V, LM74910-Q1 Only 2.5 4.2 mA
VCAP – VS Charge Pump Turn ON voltage 11 12.2 13.2 V
Charge Pump Turnoff voltage 11.9 13.2 14.1 V
V(CAP UVLO) Charge Pump UVLO voltage threshold, rising 5.4 6.6 7.9 V
Charge Pump UVLO voltage threshold, falling 4.4 5.5 6.6 V
IDEAL DIODE (A, C, DGATE)
V(A_PORR) V(A) POR threshold, rising 2.2 2.45 2.7 V
V(A_PORF) V(A) POR threshold, falling 2 2.25 2.45 V
V(AC_REG) Regulated Forward V(A)–V(C) Threshold 3.6 10.5 13.4 mV
V(AC_REV) V(A)–V(C) Threshold for Fast Reverse Current Blocking –16 –10.5 –5 mV
V(AC_FWD) V(A)–V(C) Threshold for Reverse to Forward transition 150 177 200 mV
V(DGATE) – V(A) Gate Drive Voltage 3 V < V(S) < 5 V 7 V
5 V < V(S) < 65 V 9.2 11.5 14 V
I(DGATE) Peak Gate Source current V(A) – V(C) = 100 mV, V(DGATE) – V(A) = 1 V 18.5 mA
Peak Gate Sink current V(A) – V(C) = –12 mV, V(DGATE) – V(A) = 11 V 2670 mA
Regulation sink current V(A) – V(C) = 0 V, V(DGATE) – V(A) = 11 V 5 13.5 µA
I(C) Cathode leakage Current V(A) = –14 V, V(C) = 12 V 4 9 32 µA
HIGH SIDE CONTROLLER (HGATE, OUT)
V(HGATE) – V(OUT) Gate Drive Voltage 3 V < V(S) < 5 V 7 V
5 V < V(S) < 65 V 10 11.1 14.5 V
I(HGATE) Source Current 39 55 75 µA
Sink Current V(OV) > V(OVR) 128 180 mA
SLEEP MODE
V(SLEEPR) SLEEP high threshold voltage  0.85 1.05 V
V(SLEEPF) SLEEP threshold voltage for low Iq shutdown, falling 0.41 0.7 V
I(SLEEP) SLEEP input leakage current 100 160 nA
Overvoltage threshold SLEEP mode overvoltage rising threshold SLEEP=Low, EN=High 19.3 21.3 23 V
Overvoltage threshold SLEEP mode overvoltage threshold SLEEP=Low, EN=High 18.4 21 22.2 V
Overcurrent  threshold SLEEP mode overcurrent threshold (device Latch-off) 150 250 310 mA
T(TSD) SLEEP mode TSD Threshold, rising SLEEP=Low, EN=High 155 ℃
T(TSDhyst) TSD Hysteresis SLEEP=Low, EN=High 10 ℃