Connect A, DGATE and C pins of LM74930-Q1 close to the MOSFET SOURCE, GATE and DRAIN pins for the ideal diode stage.
Connect HGATE and OUT pins of LM74930-Q1 close to the MOSFET GATE and SOURCE pins for the load disconnect stage.
Use thick and short traces for source and drain of the MOSFET to minimize resistive losses. The high current path for this design is through the MOSFET.
Connect the DGATE pin of the LM74930-Q1 to the MOSFET GATE with short trace.
Follow kelvin connection for connecting CS+ and CS- pin to external current sense resistor.
Place transient suppression components close to LM74930-Q1.
Place the decoupling capacitor, CVS, close to VS pin and chip GND.
Keep the charge pump capacitor across CAP and VS pins away from the MOSFET to lower the thermal effects on the capacitance value.
Obtaining acceptable performance with alternate layout schemes is possible, however the layout shown in the Layout Example is intended as a guideline and to produce good results.