SNAS264D April   2006  – February 2024 LM94

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Pin Configuration and Functions
    1. 4.1 Server Terminology
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Operating Ratings
    3.     11
    4. 5.3 DC Electrical Characteristics
    5. 5.4 AC Electrical Characteristics
    6.     14
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Feature Description
      1. 6.2.1  Monitoring Cycle Time
      2. 6.2.2  ΣΔ A/D Inherent Averaging
      3. 6.2.3  Temperature Monitoring
        1. 6.2.3.1 “Remote Diode” TruTherm Mode
        2. 6.2.3.2 Temperature Data Format
        3. 6.2.3.3 Thermal Diode Fault Status
      4. 6.2.4  Event Errors for Fan Boost
      5. 6.2.5  Voltage Monitoring
      6. 6.2.6  Recommended External Scaling Resistors for +12V Power Rails
      7. 6.2.7  Recommended External Scaling Circuit for −12V Power Input
      8. 6.2.8  Adding External Scaling Resistors to Other Analog Inputs
      9. 6.2.9  Dynamic Vccp Monitoring Using VID
      10. 6.2.10 Monitoring Analog Temperature Sensors
      11. 6.2.11 VREF Output
      12. 6.2.12 PROCHOT Background Information
      13. 6.2.13 PROCHOT Monitoring
      14. 6.2.14 PROCHOT Output Control
      15. 6.2.15 Fan Speed Measurement
      16. 6.2.16 Smart Fan Speed Measurement
      17. 6.2.17 Inputs/Outputs
        1. 6.2.17.1 ALERT Output
        2. 6.2.17.2 RESET Input/Output
        3. 6.2.17.3 PWM1 and PWM2 Outputs
        4. 6.2.17.4 VRD1_HOT and VRD2_HOT Inputs
        5. 6.2.17.5 GPIO and GPI PINS
        6. 6.2.17.6 Fan Tach Inputs
      18. 6.2.18 Fan Control
        1. 6.2.18.1 Automatic Fan Control Methods
        2. 6.2.18.2 LUT Fan Control Duty Cycles
        3. 6.2.18.3 Alternate LUT PWM Mapping
        4. 6.2.18.4 Fan Control Priorities
        5. 6.2.18.5 PWM to 100% Conditions
        6. 6.2.18.6 VRDx_HOT Ramp-Up/Ramp-Down
        7. 6.2.18.7 PROCHOT Ramp-Up/Ramp-Down
        8. 6.2.18.8 Manual PWM Override
        9. 6.2.18.9 Fan Spin-Up Control
      19. 6.2.19 XOR TREE TEST
    3. 6.3 Programming
      1. 6.3.1 SMBus Interface
        1. 6.3.1.1 SMBus ADDRESSING
        2. 6.3.1.2 DIGITAL NOISE EFFECT ON SMBus COMMUNICATION
        3. 6.3.1.3 GENERAL SMBus TIMING
        4. 6.3.1.4 SMBus ERROR SAFETY FEATURES
        5. 6.3.1.5 Serial Interface Protocols
          1. 6.3.1.5.1 Address Incrementing
          2. 6.3.1.5.2 Block Command Code Summary
          3. 6.3.1.5.3 Write Operations
            1. 6.3.1.5.3.1 Write Byte
            2. 6.3.1.5.3.2 Write Word
            3. 6.3.1.5.3.3 SMBus Write Block to Any Address
            4. 6.3.1.5.3.4 I2C Block Write
          4. 6.3.1.5.4 Read Operations
            1. 6.3.1.5.4.1 Read Byte
            2. 6.3.1.5.4.2 Read Word
            3. 6.3.1.5.4.3 SMBus Block-Write Block-Read Process Call
            4. 6.3.1.5.4.4 Simulated SMBus Block-Write Block-Read Process Call
            5. 6.3.1.5.4.5 SMBus Fixed Address Block Reads
            6. 6.3.1.5.4.6 I2C Block Reads
        6. 6.3.1.6 READING AND WRITING 16-BIT REGISTERS
    4. 6.4 Registers
      1. 6.4.1  Regsiter Warnings
      2. 6.4.2  Register Summary Table
      3. 6.4.3  Factory Registers 00h–04h
        1. 6.4.3.1 Register 00h XOR Test
        2. 6.4.3.2 Register 01h SMBus Test
        3. 6.4.3.3 “REMOTE DIODE” MODE SELECT
          1. 6.4.3.3.1 Register 05h Remote-Diode Transistor Mode Select
      4. 6.4.4  Value Registers Section 1
        1. 6.4.4.1 Registers 06-07h and 50–53h Unfiltered Temperature Value Registers
        2. 6.4.4.2 Registers 08–09h and 54–55h Filtered Temperature Value Registers
        3. 6.4.4.3 Register 0Ah and 0Bh PWM1 and PWM2 8-bit Duty Cycle Value
      5. 6.4.5  PWM Duty Cycle Overide Registers
        1. 6.4.5.1 Register 0Ch PWM1 Duty Cycle Override (low byte)
        2. 6.4.5.2 Register 0Dh PWM1 Duty Cycle Override (high byte)
        3. 6.4.5.3 Register 0Eh PWM2 Duty Cycle Override (low byte)
        4. 6.4.5.4 Register 0Fh PWM2 Duty Cycle Override (high byte)
      6. 6.4.6  Extended Resolution Value Registers
        1. 6.4.6.1 Registers 10h - 17h Zone 1 (CPU1) and Zone 2 (CPU2) Extended Resolution Unfiltered Temperature Value Registers, Most and Least Significant Bytes
        2. 6.4.6.2 Registers 18h – 1Fh Zone 1 (CPU1) and Zone 2 (CPU2) Extended Resolution Filtered Value Registers, Most and Least Significant Bytes
        3. 6.4.6.3 Registers 20h – 23h Zone 3 and Zone 4 Extended Resolution Value Registers, Most and Least Significant Bytes
      7. 6.4.7  PI Loop Fan Control Setup Registers
        1. 6.4.7.1  Register 31h Internal/External Temperature Source Select
        2. 6.4.7.2  Register 32h PWM Filter Settings
        3. 6.4.7.3  Register 33h PWM1 Filter Shutoff Threshold
        4. 6.4.7.4  Register 34h PWM2 Filter Shutoff Threshold
        5. 6.4.7.5  Register 35h PI/LUT Fan Control Bindings
        6. 6.4.7.6  Register 36h PI Controller Minimum PWM and Hysteresis
        7. 6.4.7.7  Registers 37h and 38h Zone 1 and 2 PI Controller Target Temperature (Tcontrol)
        8. 6.4.7.8  Register 39h and 3Ah Zone 1 and 2 PI Fan Control Off Temperature (Toff)
        9. 6.4.7.9  Register 3Bh Proportional Coefficient
        10. 6.4.7.10 Register 3Ch Integral Coefficient
        11. 6.4.7.11 Register 3Dh PI Coefficient Exponents
      8. 6.4.8  Device Identification Registers (3Eh-3Fh)
        1. 6.4.8.1 Register 3Eh Manufacturer ID
        2. 6.4.8.2 Register 3Fh Version/Stepping
      9. 6.4.9  BMC Error Status Registers 40h–47h
        1. 6.4.9.1 Register 40h B_Error Status 1
        2. 6.4.9.2 Register 41h B_Error Status 2
        3. 6.4.9.3 Register 42h B_Error Status 3
        4. 6.4.9.4 Register 43h B_Error Status 4
        5. 6.4.9.5 Register 44h B_ P1_PROCHOT Error Status
        6. 6.4.9.6 Register 45h  B_P2_PROCHOT Error Status
        7. 6.4.9.7 Register 46h B_GPI Error Status
        8. 6.4.9.8 Register 47h B_Fan Error Status
      10. 6.4.10 Host Error Status Registers
        1. 6.4.10.1 Register 48h H_Error Status 1
        2. 6.4.10.2 Register 49h H_Error Status 2
        3. 6.4.10.3 Register 4Ah H_Error Status 3
        4. 6.4.10.4 Register 4Bh H_Error Status 4
        5. 6.4.10.5 Register 4Ch  H_P1_PROCHOT Error Status
        6. 6.4.10.6 Register 4Dh  B_P2_PROCHOT Error Status
        7. 6.4.10.7 Register 4Eh H_GPI Error Status
        8. 6.4.10.8 Register 4Fh H_Fan Error Status
      11. 6.4.11 Value Registers
        1. 6.4.11.1  Registers 50–53h Unfiltered Temperature Value Registers
        2. 6.4.11.2  Registers 54–55h Filtered Temperature Value Registers
        3. 6.4.11.3  Register 56–65h A/D Channel Voltage Registers
        4. 6.4.11.4  Register 67h Current P1_PROCHOT
        5. 6.4.11.5  Register 68h Average P1_PROCHOT
        6. 6.4.11.6  Register 69h Current P2_PROCHOT
        7. 6.4.11.7  Register 6Ah Average P2_PROCHOT
        8. 6.4.11.8  Register 6Bh Current GPI State
        9. 6.4.11.9  Register 6Ch P1_VID
        10. 6.4.11.10 Register 6Dh P2_VID
        11. 6.4.11.11 Register 6E–75h Fan Tachometer Readings
      12. 6.4.12 Limit Registers
        1. 6.4.12.1 Registers 78–7Fh Temperature Limit Registers
        2. 6.4.12.2 Registers 80–83h Fan Boost Temperature Registers
        3. 6.4.12.3 Register 84h Zone1, and Zone2 Hysteresis for Limit Comparisons
        4. 6.4.12.4 Register 85h Zone3 and Zone4 Hysteresis for Limit Comparisons
        5. 6.4.12.5 Registers 8E–8Fh Zone 1b and Zone 2b Temperature Reading Adjustment Registers
        6. 6.4.12.6 Registers 90–AFh Voltage Limit Registers
        7. 6.4.12.7 Register B0–B1h  PROCHOT User Limit Registers
        8. 6.4.12.8 Register B2–B3h Dynamic Vccp Limit Offset Registers
        9. 6.4.12.9 Register B4–BBh Fan Tach Limit Registers
      13. 6.4.13 Setup Registers
        1. 6.4.13.1  Register BCh Special Function Control 1 (Voltage Hysteresis and Fan Control Filter Enable)
        2. 6.4.13.2  Register BDh Special Function Control 2 (Smart Tach Mode Enable, Fan Control Temperature Resolution Control and VID Mode Select)
        3. 6.4.13.3  Register BEh GPI/VID Level Control
        4. 6.4.13.4  Register BFh PWM Ramp Control
        5. 6.4.13.5  Register C0h Fan Boost Hysteresis (Zones 1/2)
        6. 6.4.13.6  Register C1h Fan Boost Hysteresis (Zones 3/4)
        7. 6.4.13.7  Register C2h Zones 1/2 Spike Smoothing Control
        8. 6.4.13.8  Register C3h LUT 1/2 MinPWM and Hysteresis
        9. 6.4.13.9  Register C4h LUT 3/4 MinPWM and Hysteresis
        10. 6.4.13.10 Register C5h GPO
        11. 6.4.13.11 Register C6h PROCHOT Control
        12. 6.4.13.12 Register C7h PROCHOT Time Interval
        13. 6.4.13.13 Register C8h PWM1 Control 1
        14. 6.4.13.14 Register C9h PWM1 Control 2
        15. 6.4.13.15 Register CAh PWM1 Control 3
        16. 6.4.13.16 Register CBh PWM1 Control 4
        17. 6.4.13.17 Register CCh PWM2 Control 1
        18. 6.4.13.18 Register CDh PWM2 Control 2
        19. 6.4.13.19 Register CEh PWM2 Control 3
        20. 6.4.13.20 Register CFh PWM2 Control 4
        21. 6.4.13.21 Register D0h–D3h LUT 1 to 4 Base Temperatures
        22. 6.4.13.22 Register D4h–DFh Lookup Table Steps—LUT 1/2 and LUT 3/4 Offset Temperature
        23. 6.4.13.23 Register E0h Special Function TACH to PWM Binding
        24. 6.4.13.24 Register E1h Tachometer Fan Boost Control Register
        25. 6.4.13.25 Register E2h LM94 Status Control
        26. 6.4.13.26 Register E3h LM94 Configuration
      14. 6.4.14 Sleep State Control and Mask Registers
        1. 6.4.14.1 Register E4h Sleep State Control
        2. 6.4.14.2 Register E5h S1 GPI Mask
        3. 6.4.14.3 Register E6h S1 Tach Mask
        4. 6.4.14.4 Register E7h S3 GPI Mask
        5. 6.4.14.5 Register E8h S3 Tach Mask
        6. 6.4.14.6 Register E9h S3 Temperature/Voltage Mask
        7. 6.4.14.7 Register EAh S4/5 GPI Mask
        8. 6.4.14.8 Register EBh S4/5 Temperature/Voltage Mask
      15. 6.4.15 Other Mask Registers
        1. 6.4.15.1 Register ECh GPI Error Mask
        2. 6.4.15.2 Register EDh Miscellaneous Error Mask
        3. 6.4.15.3 Register EE and EFh Zone 1a and Zone 2a Adjustment Register
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power On
      2. 7.1.2 Resets
      3. 7.1.3 Address Selection
      4. 7.1.4 Device Setup
      5. 7.1.5 Round Robin Voltage/Temperature Conversion Cycle
      6. 7.1.6 Error Status Registers
        1. 7.1.6.1 ASF Mode
      7. 7.1.7 Masking, Error Status and ALERT
      8. 7.1.8 Layout and Grounding
    2. 7.2 Typical Application
      1. 7.2.1 Thermal Diode Application
        1. 7.2.1.1 Diode Non-Ideality
          1. 7.2.1.1.1 Diode Non-Ideality Factor Effect on Accuracy
          2. 7.2.1.1.2 Calculating Total System Accuracy
          3. 7.2.1.1.3 Compensating for Different Non-Ideality
  9. 8 Layout
    1. 8.1 Recommended Implementation
    2. 8.2 PCB Layout for Minimizing Noise
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.1.5.4.4 Simulated SMBus Block-Write Block-Read Process Call

Alternatively, if the master cannot support an SMBus Block-Write Block-Read process call, it can be emulated by two transactions (a block write followed by a block read). This should only be done in a single master system, since in a dual master system collisions can occur that corrupt the data and transaction. Below is the sequence of events for these transactions:

  1. The master issues a START to start this transaction.
  2. The master sends the 7-bit slave address followed by a write bit (low).
  3. The slave asserts the ACK.
  4. The master sends the Block Read command code (F1h) and the slave asserts the ACK.
  5. The master sends the Byte Count (2h) for this transaction and the slave asserts the ACK.
  6. The master sends the Start Register Address and the slave asserts the ACK.
  7. The master sends the Byte Count (1-20h) for the Block-Read Process Call and the slave asserts the ACK.
  8. The master sends a STOP to end this transaction.
  9. The master sends a START to start this transaction.
  10. The master sends the 7-bit slave address followed by a write bit (low) and the slave asserts the ACK.
  11. The master sends the Block Read Command code (F1h) and the slave asserts the ACK.
  12. The master sends a repeat START.
  13. The master sends the 7-bit slave address followed by a read bit (high) and the slave asserts the ACK.
  14. The master receives Byte Count (this matches the size sent by the master in step 7) and asserts the ACK.
  15. The master receives Data Byte 1 and asserts the ACK.
  16. The master receives Data Byte 2 and asserts the ACK.
  17. The master receives N-3 data bytes, and asserts ACK for each one.
  18. The master receives the last data byte and asserts a NACK.
  19. The master issues a STOP to end this transaction.
12345678910∼
SSlave
Address		WABlock
Read
Command
Code (F1h)		AByte
Count
(2h)		AStart
Register
Address		AByte
Count
(1–20h)
(N)		APSSlave
Address		WA
∼1112131415161716
Block
Read
Command
Code
(F1h)		ASSlave
Address		RAByte
Count
(1–20h)
(N)		AData
Byte 1		AData
Byte 2		A∼Data
Byte N		/AP

Special Notes:

  1. Steps 9 through 19 can be repeated to read another block of data. The address auto-increments such that the next block starts where the last block left off. The size returned by the LM94 is the same each time.
  2. The LM94 returns 00h when address locations outside of normal address space are read.
  3. Block reads do not wrap around from address FFh to 00h
  4. If the master acknowledges more bytes that it requested, the LM94 continues to supply data until the master does not acknowledge a byte.
  5. If the master does not acknowledges a byte to prematurely abort a block read, the LM94 gets off the bus to allow the master to issue a STOP signal.
  6. After a block read is finished, the base address of the LM94 is updated to point to the byte just beyond the last byte read.