SNIS133E September 2003 – February 2024 LM95010
PRODUCTION DATA
This section describes master and LM95010 handling of special bus conditions, encountered during either Read or Write transactions.
If an LM95010 receives a Start Bit in the middle of a transaction, it aborts the current transaction (the LM95010 does not "complete" the current transaction) and begins a new transaction. Although not recommend for SensorPath normal operation, this situation is legitimate, therefore it is not flagged as an error by the LM95010 and Attention Request is not generated in response to it. The master generating the Start Bit, is responsible for handling the not "complete" transaction at a "higher level".
If LM95010 receives more than the expected number of data bits (defined by the size of the accessed register), it ignores the unnecessary bits. In this case, if both master and LM95010 identify correct EP and ACK bits they "complete" the transaction. However, in most cases, the additional data bits differ from the correct EP and ACK bits. In this case, both the master and the LM95010 do not "complete" the transaction. In addition, the LM95010 performs the following:
If the LM95010 receives less than the expected number of data bits (defined by the size of the accessed register), it waits indefinitely for the missing bits to be sent by the master. If then the master sends the missing bits, together with the correct EP/ACK bits, both master and LM95010 "complete" the transaction. However, if the master starts a new transaction generating a Start Bit, the LM95010 aborts the current transaction (the LM95010 does not "complete" the current transaction) and begins the new transaction. The master is not notified by the LM95010 of the incomplete transaction.