SNAS425C October   2007  – October 2014 LM98519

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Serial Interface Timing
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Clamping and Biasing Circuitry
      2. 7.3.2 Input Connections for 3 Channel Operation
      3. 7.3.3 AFE References
      4. 7.3.4 Offset Control
      5. 7.3.5 Black Level Calibration (Offset)
        1. 7.3.5.1 Manual Offset Adjustment
        2. 7.3.5.2 Automatic Offset Adjustment
        3. 7.3.5.3 Gain Control
        4. 7.3.5.4 White Level Calibration (AGC - Automatic Gain Control)
      6. 7.3.6 Operating Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 AFEPHASEn Details for SHP/SHD Input Mode
      2. 7.4.2 AFEPHASEn Details for SAMPLE and HOLD Input Mode
      3. 7.4.3 AFEPHASEn: 6 Channel and 3 Channel Modes
      4. 7.4.4 LM98519 AFEPHASE Synchronization
      5. 7.4.5 Sampling Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1  Using Black Pixel Average
      2. 7.5.2  Sample Timing Control
      3. 7.5.3  Timing Monitor Outputs
      4. 7.5.4  Output Data Test Pattern Generation
      5. 7.5.5  Fixed Pattern
      6. 7.5.6  Horizontal Gradation
      7. 7.5.7  Vertical Gradation
      8. 7.5.8  Lattice Pattern
      9. 7.5.9  Serial Interface
      10. 7.5.10 Serial Write
      11. 7.5.11 Serial Read
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
      2. 7.6.2 Configuration Register Details
  8. 8 Application and Implementation
    1. 8.1 Design Requirements
    2. 8.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Over Voltage Protection on OS Inputs
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

80-Pin
PFC Package
(Top View)
LM98519_Pinout_diagram.gif

Pin Functions(1)

PIN TYPE DESCRIPTION
NUMBER NAME
1 SHD/ HOLD DI Data Clamp Pulse
2, 54 VDDD PI Digital Power Supply
3, 7, 55 VSSD PI Digital Power Supply Ground
4 CLPIN DI Input Pulse That Invokes an Input Clamp Switch
5 BLKCLP DI Input Pulse that Invokes a Black Clamp Calibration Loop
Pulldown 108kΩ
6 IBIAS AO Optional IBIAS resistor connection. To minimize device to device power consumption variation, connect an 11k Ohm 1% resistor to VSSA. If no resistor is used, the internal bias and power supply currents will be subject to normal device to device variation.
8 AGC_ONB DI Input Pulse that Invokes the White Calibration Loop. Tie high to disable White Clamp. Pulse Low to initiate White Clamp. (Active Low)
Pulldown 108kΩ
9 MCLK DI Master Clock Input
10, 23, 35, 47 VSSO PI Output Driver Power Supply Ground
11, 24, 36, 48 VDDO PI Output Driver Power Supply
12-21 DB0–DB9 DO Bit 0 – Bit 9 of the Blue Channel
22 VREG PO Decoupling connection for VREG – Internal Voltage for Logic
25-34 DG0–DG9 DO Bit 0 – Bit 9 of the Green Channel
37-46 DR0–DG9 DO Bit 0 – Bit 9 of the Red Channel
39 DR2 (TESTO0) DO Bit 2 of Red Channel Data or TESTO0 timing monitor output (Timing monitor output selected by setting Register 0x00, Bit 1 = 1)
40 DR3 (TESTO1) DO Bit 3 of Red Channel Data or TESTO1 timing monitor output (Timing monitor output selected by setting Register 0x00, Bit 1 = 1)
49 RESETB DI Master Reset Input (Active Low)
Pulldown 108 kΩ
50 SCLK DI Serial Clock for the 4-wire Serial Interface
51 SDI DI Serial Input Data for the 4-wire Serial Interface
52 SENB DI Serial Enable (Active Low) for the 4-wire Serial Interface
Pulldown 108 kΩ
53 SDO DO Serial Output Data for the 4-wire Serial Interface
56, 65, 69, 73, 77 VSSA PI Analog Power Supply Ground
57 VREF AO Reference Voltage Bypass
58, 67, 71, 75 VDDA PI Analog Power Supply
59 VREFTOUT AO Top Reference Bypass. Connect to bypass capacitors (see applications section) and VREFTINx. – Approx. 2.23 V output(2)
60 VREFBOUT AO Bottom Reference Bypass. Connect to bypass capacitors (see applications section) and VREFBINx. – Approx. 0.98 V output(2)
61 VREFBIN2 AI Bottom Reference Input Voltage for the ADC. Connect to VREFBOUT.
62 VREFTIN2 AI Top Reference Input Voltage for the ADC. Connect to VREFTOUT.
63 VREFBIN1 AI Bottom Reference Input Voltage for the AFE. Connect to VREFBOUT.
64 VREFTIN1 AI Top Reference Input Voltage for the AFE. Connect to VREFTOUT.
66 OSR1 AI Input Voltage 1 for the Red Channel
68 OSR2 AI Input Voltage 2 for the Red Channel
70 OSG1 AI Input Voltage 1 for the Green Channel
72 OSG2 AI Input Voltage 2 for the Green Channel
74 OSB1 AI Input Voltage 1 for the Blue Channel
76 OSB2 AI Input Voltage 2 for the Blue Channel
78 VCLP_EXT AI External Clamp Voltage
79 VCLP_INT AO Internally Supplied V-Clamp Voltage
80 SHP/ SAMPLE DI Pedestal Clamp Pulse
(1) A – Analog, D – Digital, P – Power, I – Input, O – Output, PD – Pull-down resistor to VSSD, PU – Pull-up resistor to VDDD
(2) Voltages provided for debugging only. Not an ensured specification.