SNAS425C October   2007  – October 2014 LM98519

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Serial Interface Timing
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Clamping and Biasing Circuitry
      2. 7.3.2 Input Connections for 3 Channel Operation
      3. 7.3.3 AFE References
      4. 7.3.4 Offset Control
      5. 7.3.5 Black Level Calibration (Offset)
        1. 7.3.5.1 Manual Offset Adjustment
        2. 7.3.5.2 Automatic Offset Adjustment
        3. 7.3.5.3 Gain Control
        4. 7.3.5.4 White Level Calibration (AGC - Automatic Gain Control)
      6. 7.3.6 Operating Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 AFEPHASEn Details for SHP/SHD Input Mode
      2. 7.4.2 AFEPHASEn Details for SAMPLE and HOLD Input Mode
      3. 7.4.3 AFEPHASEn: 6 Channel and 3 Channel Modes
      4. 7.4.4 LM98519 AFEPHASE Synchronization
      5. 7.4.5 Sampling Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1  Using Black Pixel Average
      2. 7.5.2  Sample Timing Control
      3. 7.5.3  Timing Monitor Outputs
      4. 7.5.4  Output Data Test Pattern Generation
      5. 7.5.5  Fixed Pattern
      6. 7.5.6  Horizontal Gradation
      7. 7.5.7  Vertical Gradation
      8. 7.5.8  Lattice Pattern
      9. 7.5.9  Serial Interface
      10. 7.5.10 Serial Write
      11. 7.5.11 Serial Read
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
      2. 7.6.2 Configuration Register Details
  8. 8 Application and Implementation
    1. 8.1 Design Requirements
    2. 8.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Over Voltage Protection on OS Inputs
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

9.1 Over Voltage Protection on OS Inputs

The OS inputs are protected from damage caused by transients from the sensor circuitry during power up/down. When the chip has just been powered up, the protective clamp circuits are enabled by setting Register 0x01, Bit 4 to 1. This clamps the OS inputs to VSSA with internal PMOS devices. The protective clamp circuits are disabled by setting the OVPB enable bit to 0.

The maximum voltage and input current specifications for the OS inputs when OVP is enabled are the same as those listed in Absolute Maximum Ratings.

Positive input signals will be clamped by the internal switch through a diode to VSSA. Negative input signals will be clamped by the internal ESD protection diode to one diode drop below VSSD. Typically this will be about 0.7 V below ground.

Table 11. OVP Enable Bit Settings

OVP ENABLE BIT
(Register 0x01, Bit 4)		 OVER VOLTAGE PROTECTION
INPUT CLAMPING
0 Disabled
1 Enabled