SNAS558N January   2000  – March 2024 LMC555

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Power Dissipation
      2. 7.3.2 Various Packages and Compatibility
      3. 7.3.3 Operates in Both Astable and Monostable Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Monostable Operation
      2. 7.4.2 Astable Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Flash LED in Monostable Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Frequency Divider
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curve
      3. 8.2.3 Pulse Width Modulator
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curve
      4. 8.2.4 Pulse Position Modulator
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Application Curve
      5. 8.2.5 50% Duty Cycle Oscillator
        1. 8.2.5.1 Design Requirements
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • YPB|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Layout Example

The figure below is the basic layout for various applications.

  • C1 – based on time delay calculations
  • C2 – 0.01 µF bypass capacitor for control voltage pin
  • C3 – 0.1 µF bypass ceramic capacitor
  • C4 – 1-µF electrolytic bypass capacitor
  • R1 – based on time delay calculations
  • U1 – LMC555

GUID-20240201-SS0I-F7RV-THGN-FXPF5P12DCBQ-low.svg Figure 8-10 PCB Layout