SNOS724F August   2000  – February 2024 LMC6492 , LMC6494

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Input Common-Mode Voltage Range
      2. 6.1.2 Rail-to-Rail Output
      3. 6.1.3 Compensating for Input Capacitance
      4. 6.1.4 Capacitive Load Tolerance
    2. 6.2 Typical Application
      1. 6.2.1 Application Circuits
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Printed Circuit Board Layout For High-Impedance Work
  8. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Spice Macromodel
        2. 7.1.1.2 PSpice® for TI
        3. 7.1.1.3 TINA-TI™ Simulation Software (Free Download)
        4. 7.1.1.4 DIP-Adapter-EVM
        5. 7.1.1.5 DIYAMP-EVM
        6. 7.1.1.6 TI Reference Designs
        7. 7.1.1.7 Filter Design Tool
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4.     Trademarks
    5. 7.4 Electrostatic Discharge Caution
    6. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at TJ = +25°C, V+ = 5V, V– = 0V, VCM = VOUT = V+ / 2, and RL > 1MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC SPECS
VOS Input offset voltage   LMC649xAE  ±0.11 ±3 mV
TA = –40°C to +125°C ±3.8
LMC649xBE ±0.11 ±6
TA = –40°C to +125°C ±6.8
dVOS/dT Input offset voltage drift  TA = –40°C to +125°C ±1 µV/°C
IB Input bias current  ±0.15 pA
TA = –40°C to +125°C ±200
IOS Input offset current ±0.075 pA
TA = –40°C to +125°C ±100
CIN Common-mode input capacitance 3 pF
RIN Input resistance >10 TΩ
CMRR Common-mode rejection ratio LMC649xAE
0V ≤ VCM ≤ 15V, V+ = 15V		 65 82 dB
TA = –40°C to +125°C 60
LMC649xBE
0V ≤ VCM ≤ 15V, V+ = 15V		 63 82
TA = –40°C to +125°C 58
LMC649xAE
0V ≤ VCM ≤ 5V, V+ = 5V		 65 82
TA = –40°C to +125°C 60
LMC649xBE
0V ≤ VCM ≤ 5V, V+ = 5V		 63 82
TA = –40°C to +125°C 58
+PSRR Positive power-supply rejection ratio LMC649xAE
5V ≤ V+ ≤ 15V, V– = 0V,
VO = 2.5V		 65 82 dB
TA = –40°C to +125°C 60
LMC649xBE
5V ≤ V+ ≤ 15V, V– = 0V,
VO = 2.5V		 63 82
TA = –40°C to +125°C 58
–PSRR Negative power-supply rejection ratio LMC649xAE
–5V ≤ V– ≤ –15V, V+ = 0V,
VO = –2.5V		 65 82 dB
TA = –40°C to +125°C 60
LMC649xBE
–5V ≤ V– ≤ –15V, V+ = 0V,
VO = –2.5V		 63 82
TA = –40°C to +125°C 58
VCM Input common-mode voltage V+ = 5V and 15V,
for CMRR ≥ 50dB		 Low (V–) – 0.3 –0.25 V
Low, TA = –40°C to +125°C 0
High (V+) + 0.25 (V+) + 0.3
High, TA = –40°C to +125°C V+
AV Large-signal voltage gain Sourcing, RL = 2kΩ to 7.5V, V+ = 15V, 7.5V ≤ VO ≤ 11.5V 300 V/mV
Sinking, RL = 2kΩ to 7.5V, V+ = 15V, 3.5V ≤ VO ≤ 7.5V 40
VO Voltage output swing V+ = 5V, RL = 2kΩ to V+ / 2 Swing high 4.8 4.9 V
Swing high,
TA = –40°C to +125°C		 4.7
Swing low 0.1 0.18
Swing low,
TA = –40°C to +125°C		 0.24
V+ = 5V, RL = 600Ω to V+ / 2 Swing high 4.5 4.7
Swing high,
TA = –40°C to +125°C		 4.24
Swing low 0.3 0.5
Swing low,
TA = –40°C to +125°C		 0.65
V+ = 15V, RL = 2kΩ to V+ / 2 Swing high 14.4 14.7
Swing high,
TA = –40°C to +125°C		 14.0
Swing low 0.16 0.35
Swing low,
TA = –40°C to +125°C		 0.5
V+ = 15V, RL = 600Ω to V+ / 2 Swing high 13.4 14.1
Swing high,
TA = –40°C to +125°C		 13
Swing low 0.5 1.0
Swing low,
TA = –40°C to +125°C		 1.5
ISC Output short-circuit current V+ = 5V, sourcing, VO = 0V 16 25 mA
TA = –40°C to +125°C 10
V+ = 5V, sinking, VO = 5V 11 22
TA = –40°C to +125°C 8
V+ = 15V, sourcing, VO = 0V 28 30
TA = –40°C to +125°C 20
V+ = 15V, sinking, VO = 5V(1) 30 30
TA = –40°C to +125°C 22
IS Supply current  Per amplifier, V+ = 5V,
VO = V+ / 2		 0.5 0.875 mA
TA = –40°C to +125°C 1.05
Per amplifier, V+ = 15V,
VO = V+ / 2		 0.65 0.975
TA = –40°C to +125°C 1.15
AC SPECS
SR Slew rate(2) V+ = 15V, connected as voltage follower with 10V step 0.7 1.3 V/µs
TA = –40°C to +125°C 0.5
GBW Gain bandwidth V+ = 15V 1.5 MHz
Θm Phase margin 50 Deg
Gm Gain margin 15 dB
Amp-to-amp isolation Input referred
V+ = 15V, RL = 100kΩ to 7.5V, VO = 12VPP, f = 1kHz		 150 dB
en Input-referred voltage noise f = 1kHz, VCM = 1V 37 nV/√Hz
in Input current noise density f = 1kHz 0.06 pA/√Hz
THD Total harmonic distortion f = 1kHz, AV = –2, RL = 10kΩ, VO = –4.1VPP 0.01 %
f = 10kHz, AV = –2, RL = 10kΩ, VO = 8.5VPP, V+ = 10V 0.01
(1) Do not short circuit output to V+ when V+ is greater than 13V or reliability is adversely affected.
(2) Specification established from device population bench system measurements across multiple lots. Number specified is the slower of either the positive or negative slew rates.