SNOSD74C May   2019  – December 2024 LMG1025-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Output Stage
      3. 6.3.3 Bias Supply and Under Voltage Lockout
      4. 6.3.4 Overtemperature Protection (OTP)
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Handling Ground Bounce
        2. 7.2.2.2 Creating Nanosecond Pulse
        3. 7.2.2.3 VDD and Overshoot
        4. 7.2.2.4 Operating at Higher Frequency
      3. 7.2.3 Application Curves
  9. Power Supply Recommendations
  10. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Gate Drive Loop Inductance and Ground Connection
      2. 9.1.2 Bypass Capacitor
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Trademarks
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DEE|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overview

LMG1025-Q1 is a high-performance low-side 5-V gate driver for GaN and logic-level MOSFETs. While it is designed to function well in high-speed applications, such as wireless power transmission and LiDAR/ToF, it can be used in any application where a low-side gate driver is required. The LMG1025-Q1 is optimized to provide the lowest propagation delay through the driver to the power transistor. LMG1025-Q1 is in a small 2mm×2mm QFN package with wettable flanks, in order to minimize its parasitic inductance. This low inductance design is necessary to achieve high current, low ringing performance in very high frequency operation when driving power FETs. The same holds true for when designing with LMG1025-Q1. QFN package with wettable flanks is also needed to improve system robustness in many automotive applications.