SNOSD37B march 2017 – april 2023 LMG1205
PRODUCTION DATA
The circuit in Figure 8-1 shows a synchronous buck converter to evaluate LMG1205. Detailed synchronous buck converter specifications are listed in Section 8.2.1. Optimization of he power loop (loop impedance from VIN capacitor to PGND) is critical to the performance of the design. Having a high power loop inductance causes significant ringing in the SW node and also causes an associated power loss. For more information, please refer to Section 11.2.1.