SNOSD12D November   2018  – January 2019 LMG1210

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
    8. 6.8 Timing Diagrams
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bootstrap Diode Operation
      2. 7.3.2 LDO Operation
      3. 7.3.3 Dead Time Selection
      4. 7.3.4 Overtemperature Protection
      5. 7.3.5 High-Performance Level Shifter
      6. 7.3.6 Negative HS Voltage Handling
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Bypass Capacitor
        2. 8.2.2.2 Bootstrap Diode Selection
        3. 8.2.2.3 Handling Ground Bounce
        4. 8.2.2.4 Independent Input Mode
        5. 8.2.2.5 Computing Power Dissipation
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RVR|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1 Bypass Capacitor

To properly drive the GaN FETs, TI recommends placing high-quality ceramic bypass capacitors as close as possible between the HB to HS and VDD to VSS. If using the LDO, the VDD-VSS capacitor is required to be at least 0.3 µF at bias for stability. However, a larger capacitor may be required for many applications.

The bootstrap capacitor must be large enough to support charging the high-side FET and supplying the high-side quiescent current when the high-side FET is on. The required capacitance can be calculated as Equation 7:

Equation 7. (0.5 nC + Qrr + QgH + IHB × ton)/ΔV = CBST,min

where

  • QgH is the gate charge of the high-side GaN FET,
  • IHB is the quiescent current of the high-side driver,
  • tON is the maximum on time period of the high side,
  • Qrr is the reverse recovery of the bootstrap diode,
  • 0.5 nC is the additional charge per cycle removed from the bootstrap due to high side dynamic current,
  • and ΔV is the acceptable droop on the bootstrap capacitor voltage.

When using larger bootstrap capacitors, TI recommends that the VDD-VSS capacitor also be increased to keep the ratio at least 5 to 1. If this is not maintained, the charging of the bootstrap capacitor can pull the VDD-VSS rail down sufficiently to cause UVLO conditions and potentially unwanted behavior.