SNOSDJ1 July   2024 LMG2100R026

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-Up and UVLO
      3. 7.3.3 Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Slew Rate Control
        4. 8.2.2.4 Power Dissipation
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
  • VBN|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 VBN Package, 18-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
NC 1–4, 8, 9, 16 — Not connected internally. Leave floating.
SW 5 P Switching node. Internally connected to HS pin.
PGND 6, 17, 18 G Power ground. Low-side GaN FET source. Internally connected to low-side GaN FET source.
VIN 7 P Input voltage pin. Internally connected to high-side GaN FET drain.
HB 10 P High-side gate driver bootstrap rail. Connect bypass capacitor to HS.
HS 11 P High-side GaN FET source connection.
HI 12 I High-side gate driver control input.
LI 13 I Low-side gate driver control input.
VCC 14 P 5V device power supply.
AGND 15 G Analog ground. Internally connected to low-side GaN FET source.
(1) I = Input, O = Output, G = Ground, P = Power