SNOSDI8 May   2024 LMG2650

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Turn-On Slew-Rate Control
      3. 7.3.3  Current-Sense Emulation
      4. 7.3.4  Bootstrap Diode Function
      5. 7.3.5  Input Control Pins (EN, INL, INH, GDH)
      6. 7.3.6  INL - INH Interlock
      7. 7.3.7  AUX Supply Pin
        1. 7.3.7.1 AUX Power-On Reset
        2. 7.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 7.3.8  BST Supply Pin
        1. 7.3.8.1 BST Power-On Reset
        2. 7.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RFB|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8.2 BST Under-Voltage Lockout (UVLO)

The BST UVLO voltage is with respect to the SW pin. The BST UVLO blocks both the INH and GDH pins from turning on the high-side GaN power FET if the BST-to-SW voltage is below the applicable BST UVLO voltage as described as follows. Figure 7-3 shows the BST UVLO blocking operation. The BST UVLO consists of two separate UVLO functions to create a two-level BST UVLO. The upper BST UVLO is called the BST Turn-On UVLO and only controls if the high-side GaN power FET is allowed to turn on. The lower BST UVLO is called the BST Turn-Off UVLO and only controls if the high-side GaN power FET is turned off after the high-side GaN power FET is already turned on. The operation of the two-level UVLO is not the same as a single UVLO with hysteresis.

Figure 7-4 shows the two-level BST UVLO operation. The BST Turn-On UVLO prevents the high-side GaN power FET from turning on, for INH or GDH logic-high, if the BST-to-SW voltage is below the BST Turn-On UVLO voltage (INH/GDH pulse #1, first portion of pulse #2, and pulse #5). After the high-side GaN power FET is successfully turned-on, the BST Turn-On UVLO is ignored and the BST Turn-Off UVLO output is watched for the remainder of the INH or GDH logic-high pulse (INH/GDH second portion of pulse #2, pulses #3, #4, and #6. The BST Turn-Off UVLO turns off the high-side GaN power FET for the remainder of the INH/GDH logic-high pulse if the BST-to-SW voltage falls below the BST Turn-Off UVLO voltage (INH/GDH pulse #6).


LMG2650 BST UVLO Operation

Figure 7-4 BST UVLO Operation

The effective voltage hysteresis of the two-level BST UVLO is the difference between the upper and lower BST UVLO voltages. A single-level BST UVLO can be implemented with the same hysteresis but allows subsequent high-side GaN power FET turn on anywhere in the hysteresis range. A single-level BST UVLO allows INH/GDH pulse #5 to turn on the high-side GaN power. The two-level UVLO design prevents any turn on in the hysteresis range.

The two-level BST UVLO allows a wide hysteresis while making sure the BST-to-SW capacitor is adequately charged at the beginning of every INH or GDH pulse. The wide hysteresis allows a smaller BST-to-SW capacitor to be used which is useful for faster high-side start-up time. The adequate capacitor charge at the beginning of the INH or GDH pulse helps make sure the high-side GaN power FET is not turned-off early in the INH or GDH pulse which can create erratic converter operation.