SNOSDI8 May   2024 LMG2650

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Turn-On Slew-Rate Control
      3. 7.3.3  Current-Sense Emulation
      4. 7.3.4  Bootstrap Diode Function
      5. 7.3.5  Input Control Pins (EN, INL, INH, GDH)
      6. 7.3.6  INL - INH Interlock
      7. 7.3.7  AUX Supply Pin
        1. 7.3.7.1 AUX Power-On Reset
        2. 7.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 7.3.8  BST Supply Pin
        1. 7.3.8.1 BST Power-On Reset
        2. 7.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RFB|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Turn-On Slew-Rate Control

The turn-on slew rate of both the low-side and high-side GaN power FETs are individually programmed to one of four discrete settings. The low-side slew rate is programmed by the resistance between the RDRVL and AGND pins. The high-side slew rate is programmed by the resistance between the RDRVH and SW pins. The low-side slew-rate setting is determined one time during AUX power up when the AUX voltage goes above the AUX power-on reset voltage. The high-side slew-rate setting is determined one time during BST-to-SW power up when the BST-to-SW voltage goes above the BST power-on reset voltage. The slew-rate setting determination time is not specified but is around 0.4µs.

Table 7-1 shows the recommended typical resistance programming value for the four slew rate settings and the typical turn-on slew rate at each setting. As noted in the table, an open-circuit connection is acceptable for programming slew-rate setting 0 and a short-circuit connection (RDRVL shorted to AGND for the low-side turn-on slew rate) (RDRVH shorted to SW for the high-side turn-on slew rate) is acceptable for programming slew-rate setting 3.

Table 7-1 Slew-Rate Setting
TURN-ON SLEW RATE SETTING RECOMMENDED TYPICAL PROGRAMMING RESISTANCE

(kΩ)

 TYPICAL TURN-ON SLEW RATE

(V/ns)

 COMMENT
0 120 2 Open-circuit connection for programming resistance is acceptable.
1 47 9
2 22 50
3 5.6 80 Short-circuit connection for programming resistance (RDRVL shorted to AGND for low-side slew rate) (RDRVH shorted to SW for high-side slew rate) is acceptable.