The LMG2650 implements cycle-by-cycle overcurrent protection for both half-bridge GaN power FETs. Figure 7-5 shows the cycle-by-cycle overcurrent operation. Every INL or INH or GDH logic-high cycle turns on the controlled GaN power FET. If the GaN power FET drain current exceeds the overcurrent threshold current, the overcurrent protection turns off the GaN power FET for the remainder of the INL or INH or GDH logic-high duration.

Figure 7-5 Cycle-by-Cycle Overcurrent Protection Operation

An overcurrent protection event is not reported on the FLT pin. Cycle-by-cycle overcurrent protection minimizes system disruption because the event is not reported and because the protection allows the GaN power FET to turn on every INL or INH or GDH cycle.

As described in the Current-Sense Emulation section, an artificial CS pin current is produced after the low-side GaN power FET is turned off by the low-side overcurrent protection in order to prevent the controller from entering a hung state.