SNOSDI8 May   2024 LMG2650

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Turn-On Slew-Rate Control
      3. 7.3.3  Current-Sense Emulation
      4. 7.3.4  Bootstrap Diode Function
      5. 7.3.5  Input Control Pins (EN, INL, INH, GDH)
      6. 7.3.6  INL - INH Interlock
      7. 7.3.7  AUX Supply Pin
        1. 7.3.7.1 AUX Power-On Reset
        2. 7.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 7.3.8  BST Supply Pin
        1. 7.3.8.1 BST Power-On Reset
        2. 7.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RFB|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

1) Symbol definitions: VDS(ls) = SW to SL voltage; IDS(ls) = SW to SL current; VDS(hs) = DH to SW voltage; ID(hs) = DH to SW current; ISW = SW point current into device; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; VDS(ls) = 520V; VDS(hs) = 520V; 10V ≤ VAUX ≤ 26V; 7.5V ≤ VBST_SW ≤ 26V; VEN = 5V; VINL = 0V; VINH = 0V; RRDRVL = 0Ω; RRDRVH_SW = 0Ω; RCS = 100Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOW-SIDE GAN POWER FET
td(on)(Idrain)(ls) Drain current turn-on delay time From VINL > VINL,IT+ to ID(ls) > 50mA, VBUS = 400V, ISW = 2.65A, at following low-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) TBD ns
slew rate setting 1 TBD
slew rate setting 2 TBD
slew rate setting 3 (fastest) TBD
td(on)(ls) Turn-on delay time From VINL > VINL,IT+ to VDS(ls) < 390V, VBUS = 400V, ISW = 2.65A, at following low-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) TBD ns
slew rate setting 1 TBD
slew rate setting 2 TBD
slew rate setting 3 (fastest) TBD
tr(on)(ls) Turn-on rise time From VDS(ls) < 320V to VDS(ls) < 80V, VBUS = 400V, ISW = 2.65A, at following low-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 96 ns
slew rate setting 1 26.7
slew rate setting 2 4.8
slew rate setting 3 (fastest) 3
td(off)(ls) Turn-off delay time From VINL < VINL,IT– to VDS(ls) > 80V, VBUS = 400V, ISW = 2.65A, (independent of slew rate setting), see GaN Power FET Switching Parameters 40 ns
tf(off)(ls) Turn-off fall time From VDS(ls) > 80V to VDS(ls) > 320V, VBUS = 400V, ISW = 2.65A, (independent of slew rate setting), see GaN Power FET Switching Parameters 10 ns
Turn-on slew rate From VDS(ls) < 320V to VDS(ls) < 80V, TJ = 25℃, VBUS = 400V, ISW = 2.65A, at following low-side slew rate settings, see GaN Power FET Switching Parameters V/ns
slew rate setting 0 (slowest) 2.5 V/ns
slew rate setting 1 9
slew rate setting 2 50
slew rate setting 3 (fastest) 80
HIGH-SIDE GAN POWER FET
td(on)(Idrain)(hs,INH) Drain current turn-on delay time From VINH > VINH,IT+ to ID(hs) > 50mA, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) TBD ns
slew rate setting 1 TBD
slew rate setting 2 TBD
slew rate setting 3 (fastest) TBD
td(on)(Idrain)(hs,GDH) Drain current turn-on delay time From VGDH > VGDH,IT+ to ID(hs) > 50mA, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) TBD ns
slew rate setting 1 TBD
slew rate setting 2 TBD
slew rate setting 3 (fastest) TBD
td(on)(hs,INH) Turn-on delay time From VINH > VINH,IT+ to VDS(hs) < 390V, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) TBD ns
slew rate setting 1 TBD
slew rate setting 2 TBD
slew rate setting 3 (fastest) TBD
td(on)(hs,GDH) Turn-on delay time From VGDH > VGDH,IT+ to VDS(hs) < 390V, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) TBD ns
slew rate setting 1 TBD
slew rate setting 2 TBD
slew rate setting 3 (fastest) TBD
tr(on)(hs) Turn-on rise time From VDS(hs) < 320V to VDS(hs) < 80V, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 96 ns
slew rate setting 1 26.7
slew rate setting 2 4.8
slew rate setting 3 (fastest) 3
td(off)(hs,INH) Turn-off delay time From VINH < VINH,IT– to VDS(hs) > 80V, VBUS = 400V, ISW = –2.65A, (independent of slew rate setting), see GaN Power FET Switching Parameters 60 ns
td(off)(hs,GDH) Turn-off delay time From VGDH < VGDH,IT– to VDS(hs) > 80V, VBUS = 400V, ISW = –2.65A, (independent of slew rate setting), see GaN Power FET Switching Parameters 50 ns
tf(off)(hs) Turn-off fall time From VDS(hs) > 80V to VDS(hs) > 320V, VBUS = 400V, ISW = –2.65A, (independent of slew rate setting), see GaN Power FET Switching Parameters 10 ns
Turn-on slew rate From VDS(hs) < 320V to VDS(hs) < 80V, TJ = 25℃, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 2.5 V/ns
slew rate setting 1 9
slew rate setting 2 50
slew rate setting 3 (fastest) 80
CS
tr Rise time From ICS(src) > 0.2 × ICS(src)(final) to ICS(src) > 0.9 × ICS(src)(final), 0V ≤ VCS ≤ 2V, Low-side enabled into a 2.65A load 30 ns
EN
EN wake-up time From VEN > VIT+ to ID(ls) > 10mA, VINL = 5V 1.5 µs
BST
Start-up time from deep BST to SW discharge From VBST_SW > VBST_SW,T+(UVLO) to high-side reacts to INH or GDH high level with VBST_SW rising from 0V to 10V in 1µs 5 µs
Start-up time from shallow BST to SW discharge From VBST_SW > VBST_SW,T+(UVLO) to high-side reacts to INH or GDH high level with VBST_SW rising from 5V to 10V in 0.5µs 2.6 µs