SNOSD81B September   2018  – January 2020 LMG3410R050 , LMG3411R050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
      2.      Switching Performance at >100 V/ns
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-on Delays
      2. 7.1.2 Turn-off Delays
      3. 7.1.3 Drain Slew Rate
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Direct-Drive GaN Architecture
      2. 8.3.2 Internal Buck-Boost DC-DC Converter
      3. 8.3.3 Internal Auxiliary LDO
      4. 8.3.4 Start Up Sequence
      5. 8.3.5 R-C Decoupling for IN pin
      6. 8.3.6 Low Power Mode
      7. 8.3.7 Fault Detection
        1. 8.3.7.1 Over-current Protection
        2. 8.3.7.2 Over-Temperature Protection and UVLO
      8. 8.3.8 Drive Strength Adjustment
    4. 8.4 Safe Operation Area (SOA)
      1. 8.4.1 Repetitive SOA
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Using an Isolated Power Supply
    2. 10.2 Using a Bootstrap Diode
      1. 10.2.1 Diode Selection
      2. 10.2.2 Managing the Bootstrap Voltage
      3. 10.2.3 Reliable Bootstrap Start-up
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Loop Inductance
      2. 11.1.2 Signal Ground Connection
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Switch-Node Capacitance
      5. 11.1.5 Signal Integrity
      6. 11.1.6 High-Voltage Spacing
      7. 11.1.7 Thermal Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7.1 Over-current Protection

The OCP circuit monitors the LMG341xR050's drain current and compares that current signal with an internally set limit. Upon detection of the over-current, the family of GaN FETs has two optional protection actions: 1) latched overcurrent protection; and 2) cycle-by-cycle overcurrent protection.

LMG3410R050 provides latched OCP option, by which the FET is shut off and held off until the fault is reset by either holding the IN pin low for more than 350 μs or removing power from VDD. The timing sequence is shown in Figure 18.

LMG3411R050 provides cycle-by-cycle OCP option. In this mode, the FET is also shut off when overcurrent happens, but the output fault signal will clear after the input PWM goes low. In the next cycle, the FET can turn on as normal. The cycle-by-cycle function can be used in cases where steady state operation current is below the OCP level but transient response can still reach high current, while the circuit operation cannot be paused. It also prevents the power stage from overheating by having overcurrent induced conduction loss.

During cycle-by-cycle operation, after the current reaches the upper limit but the PWM input is still high, the load current can flow through the third-quadrant of the other FET of a half-bridge with no synchronous rectification. The extra high negative voltage drop (–5 V to –7 V) from drain to source could lead to high third-quadrant loss, similar to dead time loss but with much longer time. An operation scheme of cycle-by-cycle current limitation is shown as Figure 19. Therefore, it is critical to design the control scheme to make sure the number of switching cycles in cycle-by-cycle mode is limited, or to change PWM input based on the fault signal to shorten the time in third-quadrant conduction mode of the power stage.

OCP circuit has a 55 ns typical blanking time at slew rate of 100 V/ns to prevent false triggering during switch node transitions. The blanking time increases with respect to lower slew rates accordingly since lower slew rates results in longer switching transition time. This fast response OCP circuit protects the GaN device even under a hard short-circuit condition.

LMG3410R050 LMG3411R050 Timing_OC-Fault.gifFigure 18. OC latching and reset sequence
LMG3410R050 LMG3411R050 CBC.gifFigure 19. Cycle-by-cycle OCP Operation