SNOSDA7F September 2020 – August 2024 LMG3422R030 , LMG3426R030 , LMG3427R030
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The gate drive loop impedance must be minimized to obtain good performance. Although the gate driver is integrated on package, the bypass capacitance for the driver is placed externally. As the GaN device is turned off to a negative voltage, the impedance of the path to the external VNEG capacitor is included in the gate drive loop. The VNEG capacitor must be placed close to VNEG and GND pins.
The VDD pin bypass capacitors, C1 and C11, must also be placed close to the VDD pin with low impedance connections.