SNOSDA7F September 2020 – August 2024 LMG3422R030 , LMG3426R030
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The allowed repetitive SOA for the LMG342xR030 (Figure 5-12) is defined by the peak drain current (IDS) and the drain to source voltage (VDS) of the device during turn on. The peak drain current during switching is the sum of several currents going into drain terminal: the inductor current (Iind); the current required to charge the COSS of the other GaN device in the totem pole; and the current required to charge the parasitic capacitance (Cpar) on the switching node. 285pF is used as an average COSS of the device during switching. The parasitic capacitance on the switch node may be estimated by using the overlap capacitance of the PCB. A boost topology is used for the SOA testing. The circuit shown in Figure 6-5 is used to generate the SOA curve in Figure 5-12. For reliable operation, the junction temperature of the device must also be limited to 125°C. The IDS of Figure 5-12 can be calculated by:
where drain slew rate at the peak current is estimated between 70% and 30% of the bus voltage, and Cpar is the parasitic board capacitance at the switched node.
Refer to Achieving GaN Products With Lifetime Reliability for more details.