The LMG3425R030 GaN FET with integrated driver and protection is targeted at switch-mode power converters and enables designers to achieve new levels of power density and efficiency.
The LMG3425R030 integrates a silicon driver that enables switching speed up to 150V/ns. TI’s integrated precision gate bias results in higher switching SOA compared to discrete silicon gate drivers. This integration, combined with TI's low-inductance package, delivers clean switching and minimal ringing in hard-switching power supply topologies. Adjustable gate drive strength allows control of the slew rate from 20V/ns to 150V/ns, which can be used to actively control EMI and optimize switching performance.
Advanced power management features include digital temperature reporting, fault detection, and ideal diode mode. The temperature of the GaN FET is reported through a variable duty cycle PWM output, which simplifies managing device loading. Faults reported include overcurrent, short-circuit, overtemperature, VDD UVLO, and high-impedance RDRV pin. Ideal diode mode reduces third-quadrant losses by enabling dead-time control.
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) |
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LMG3425R030 | RQZ (VQFN, 54) | 12.00mm × 12.00mm |
PIN | TYPE(1) | DESCRIPTION | |
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NAME | NO. | ||
NC1 | 1, 16 | — | Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to DRAIN. |
DRAIN | 2–15 | P | GaN FET drain. Internally connected to NC1. |
NC2 | 17, 54 | — | Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to SOURCE, GND, and THERMAL PAD. |
SOURCE | 18–40 | P | GaN FET source. Internally connected to GND, NC2, and THERMAL PAD. |
VNEG | 41–42 | P | Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode GaN FET. Bypass to ground with a 2.2µF capacitor. |
BBSW | 43 | P | Internal buck-boost converter switch pin. Connect an inductor from this point to ground. |
GND | 44, 45, 49 | G | Signal ground. Internally connected to SOURCE, NC2, and THERMAL PAD. |
VDD | 46 | P | Device input supply. |
IN | 47 | I | CMOS-compatible non-inverting input used to turn the FET on and off. |
FAULT | 48 | O | Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details. |
OC | 50 | O | Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault Detection for details. |
TEMP | 51 | O | Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9kHz pulsed waveform. The device temperature is encoded as the duty cycle of the waveform. |
RDRV | 52 | I | Drive-strength selection pin. Connect a resistor from this pin to GND to set the turn-on drive strength to control slew rate. Tie the pin to GND to enable 150V/ns and tie the pin to LDO5V to enable 100V/ns. |
LDO5V | 53 | P | 5V LDO output for external digital isolator. |
THERMAL PAD | — | — | Thermal pad. Internally connected to SOURCE, GND, and NC2. The thermal pad can be used to conduct rated device current. |