SNOSDI3 March 2024 LMG3425R030
PRODUCTION DATA
Figure 7-8 shows the start up sequence of LMG3425R030.
Time interval A: VDD starts to build up. FAULT signal is initially pulled low.
Time interval B: After VDD passes the UVLO threshold VVDD,T+(UVLO), both LDO5V and VNEG start to built up. In a typical case where CLDO5V = 100nF and CVNEG = 2.2μF, LDO5V reaches its UVLO threshold earlier than VNEG. The start-up time may vary if different capacitors are utilized. If VDD has some glitches and falls below UVLO threshold VVDD,T-(UVLO) in this time interval, LDO5V and VNEG will stop building up and only resume when VDD goes above VVDD,T+(UVLO) again. A longer start-up time is expected in this case.
Time interval C: After LDO5V and VNEG both reach their thresholds, the FAULT signal is cleared (pulled high) and the device is able to switch following the IN pin signal.