SNOSDA7F September 2020 – August 2024 LMG3422R030 , LMG3426R030
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Figure 6-3 defines the switching timings related to the zero-voltage detection (ZVD) block, and the device’s drain-to-source voltage, IN pin signal, and ZVD output signals are demonstrated. When the device achieves zero-voltage switching (ZVS), the ZVD pin outputs a pulse-signal with width TWD_ZVD, and the delay time in between IN pin’s rising edge and ZVD pulse’s rising edge is defined as TDL_ZVD. A certain third quadrant conduction time is required to allow the device detecting a zero-voltage switching, and T3rd_ZVD indicates this timing. See the Zero-Voltage Detection (ZVD) section for more information about the ZVD timing parameters.