SNOSDA8C October   2020  – February 2024 LMG3422R050 , LMG3426R050

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switching Parameters
      1. 6.1.1 Turn-On Times
      2. 6.1.2 Turn-Off Times
      3. 6.1.3 Drain-Source Turn-On Slew Rate
      4. 6.1.4 Turn-On and Turn-Off Switching Energy
      5. 6.1.5 Zero-Voltage Detection Times
    2. 6.2 Safe Operation Area (SOA)
      1. 6.2.1 Repetitive SOA
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 LMG3422R050 Functional Block Diagram
      2. 7.2.2 LMG3426R050 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN FET Operation Definitions
      2. 7.3.2  Direct-Drive GaN Architecture
      3. 7.3.3  Drain-Source Voltage Capability
      4. 7.3.4  Internal Buck-Boost DC-DC Converter
      5. 7.3.5  VDD Bias Supply
      6. 7.3.6  Auxiliary LDO
      7. 7.3.7  Fault Protection
        1. 7.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 7.3.7.2 Overtemperature Shutdown Protection
        3. 7.3.7.3 UVLO Protection
        4. 7.3.7.4 High-Impedance RDRV Pin Protection
        5. 7.3.7.5 Fault Reporting
      8. 7.3.8  Drive-Strength Adjustment
      9. 7.3.9  Temperature-Sensing Output
      10. 7.3.10 Ideal-Diode Mode Operation
        1. 7.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
      11. 7.3.11 Zero-Voltage Detection (ZVD)
    4. 7.4 Start-Up Sequence
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Slew Rate Selection
        2. 8.2.2.2 Signal Level-Shifting
        3. 8.2.2.3 Buck-Boost Converter Design
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Using an Isolated Power Supply
      2. 8.4.2 Using a Bootstrap Diode
        1. 8.4.2.1 Diode Selection
        2. 8.4.2.2 Managing the Bootstrap Voltage
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Solder-Joint Reliability
        2. 8.5.1.2 Power-Loop Inductance
        3. 8.5.1.3 Signal-Ground Connection
        4. 8.5.1.4 Bypass Capacitors
        5. 8.5.1.5 Switch-Node Capacitance
        6. 8.5.1.6 Signal Integrity
        7. 8.5.1.7 High-Voltage Spacing
        8. 8.5.1.8 Thermal Recommendations
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Export Control Notice
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RQZ|54
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 LMG3422R050RQZ Package,54-Pin VQFN(Top View)


Figure 4-2 LMG3426R050 RQZ Package, 54-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME LMG3422R050 LMG3426R050
NC1 1, 16 1, 16 — Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to DRAIN.
DRAIN 2–15 2–15 P GaN FET drain. Internally connected to NC1.
NC2 17, 54 17, 54 — Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to SOURCE, GND, and THERMAL PAD.
SOURCE 18–40 18–40 P GaN FET source. Internally connected to GND, NC2, and THERMAL PAD.
VNEG 41–42 41–42 P Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode GaN FET. Bypass to ground with a 2.2µF capacitor.
BBSW 43 43 P Internal buck-boost converter switch pin. Connect an inductor from this point to ground.
GND 44, 45, 49 44, 45, 49 G Signal ground. Internally connected to SOURCE, NC2, and THERMAL PAD.
VDD 46 46 P Device input supply.
IN 47 47 I CMOS-compatible non-inverting input used to turn the FET on and off.
FAULT 48 48 O Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details.
OC 50 — O Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault Detection for details.
ZVD — 50 O Push-pull digital output that provides zero-voltage detection signal to indicate if device achieves zero-voltage switching in current switching cycle. Refer to Section 7.3.11 for details.
TEMP 51 51 O Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9kHz pulsed waveform. The device temperature is encoded as the duty cycle of the waveform.
RDRV 52 52 I Drive-strength selection pin. Connect a resistor from this pin to GND to set the turn-on drive strength to control slew rate. Tie the pin to GND to enable 150V/ns and tie the pin to LDO5V to enable 100V/ns.
LDO5V 53 53 P 5V LDO output for external digital isolator.
THERMAL PAD — — — Thermal pad. Internally connected to SOURCE, GND, and NC2. The thermal pad can be used to conduct rated device current.
(1) I = input, O = output, P = power, G = ground