SNOSDA8C
October 2020 – February 2024
LMG3422R050
,
LMG3426R050
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Characteristics
6
Parameter Measurement Information
6.1
Switching Parameters
6.1.1
Turn-On Times
6.1.2
Turn-Off Times
6.1.3
Drain-Source Turn-On Slew Rate
6.1.4
Turn-On and Turn-Off Switching Energy
6.1.5
Zero-Voltage Detection Times
6.2
Safe Operation Area (SOA)
6.2.1
Repetitive SOA
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.2.1
LMG3422R050 Functional Block Diagram
7.2.2
LMG3426R050 Functional Block Diagram
7.3
Feature Description
7.3.1
GaN FET Operation Definitions
7.3.2
Direct-Drive GaN Architecture
7.3.3
Drain-Source Voltage Capability
7.3.4
Internal Buck-Boost DC-DC Converter
7.3.5
VDD Bias Supply
7.3.6
Auxiliary LDO
7.3.7
Fault Protection
7.3.7.1
Overcurrent Protection and Short-Circuit Protection
7.3.7.2
Overtemperature Shutdown Protection
7.3.7.3
UVLO Protection
7.3.7.4
High-Impedance RDRV Pin Protection
7.3.7.5
Fault Reporting
7.3.8
Drive-Strength Adjustment
7.3.9
Temperature-Sensing Output
7.3.10
Ideal-Diode Mode Operation
7.3.10.1
Overtemperature-Shutdown Ideal-Diode Mode
7.3.11
Zero-Voltage Detection (ZVD)
7.4
Start-Up Sequence
7.5
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Slew Rate Selection
8.2.2.2
Signal Level-Shifting
8.2.2.3
Buck-Boost Converter Design
8.2.3
Application Curves
8.3
Do's and Don'ts
8.4
Power Supply Recommendations
8.4.1
Using an Isolated Power Supply
8.4.2
Using a Bootstrap Diode
8.4.2.1
Diode Selection
8.4.2.2
Managing the Bootstrap Voltage
8.5
Layout
8.5.1
Layout Guidelines
8.5.1.1
Solder-Joint Reliability
8.5.1.2
Power-Loop Inductance
8.5.1.3
Signal-Ground Connection
8.5.1.4
Bypass Capacitors
8.5.1.5
Switch-Node Capacitance
8.5.1.6
Signal Integrity
8.5.1.7
High-Voltage Spacing
8.5.1.8
Thermal Recommendations
8.5.2
Layout Examples
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Export Control Notice
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RQZ|54
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snosda8c_oa
snosda8c_pm
1
Features
Qualified for JEDEC JEP180 for hard-switching topologies
600
V GaN-on-Si FET with integrated gate driver
Integrated high precision gate bias voltage
200V/ns FET hold-off
3.6
MHz switching frequency
20
V/ns to 150V/ns slew rate for optimization of switching performance and EMI mitigation
Operates from 7.5V to 18V supply
Robust protection
Cycle-by-cycle overcurrent and latched short-circuit protection with < 100ns response
Withstands 720V surge while hard-switching
Self-protection from internal overtemperature and UVLO monitoring
Advanced power management
Digital temperature PWM output
LMG3426R050
includes zero-voltage detection (ZVD) feature that facilitates soft-switching converters