The LMG342xR050 uses a series Si FET to ensure the power IC stays off when VDD bias power is not applied. When the VDD bias power is off, the series Si FET is interconnected with the GaN device in a cascode mode, which is shown in the Functional Block Diagram. The gate of the GaN device is held within a volt of the series Si FET's source. When a high voltage is applied on the drain and the silicon FET blocks the drain voltage, the V_GS of the GaN device decreases until the GaN device passes the threshold voltage. Then, the GaN device is turned off and blocks the remaining major part of drain voltage. There is an internal clamp to make sure that the V_DS of the Si FET does not exceed its maximum rating. This feature avoids the avalanche of the series Si FET when there is no bias power.

When LMG342xR050 is powered up with VDD bias power, the internal buck-boost converter generates a negative voltage (V_VNEG) that is sufficient to directly turn off the GaN device. In this case, the series Si FET is held on and the GaN device is gated directly with the negative voltage.

Comparing with traditional cascode drive GaN architecture, where the GaN gate is grounded and the Si MOSFET gate is being driven to control the GaN device, direct-drive configuration has multiple advantages. First, as the Si MOSFET does need to switch in every switching cycle, GaN gate-to-source charge (Q_GS) is lower and there’s no Si MOSFET reverse-recovery related losses. Second, the voltage distribution between the GaN and Si MOSFET in off-mode in a cascode configuration can cause the MOSFET to avalanche due to high GaN drain-to-source capacitance (C_DS). Finally, the switching slew rate in direct-drive configuration can be controlled while cascode drive cannot. More information about the direct-drive GaN architecture can be found in Direct-drive configuration for GaN devices.