SLUSFB9 November   2023 LMG3612

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Turn-On Slew-Rate Control
      3. 7.3.3 Input Control Pin (IN)
      4. 7.3.4 AUX Supply Pin
        1. 7.3.4.1 AUX Power-On Reset
        2. 7.3.4.2 AUX Under-Voltage Lockout (UVLO)
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Turn-On Slew-Rate Design
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REQ|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

1) Symbol definitions: ID = D to S current;  IS = S to D current;  2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; 10 V ≤ VAUX ≤ 26 V; VIN = 0 V; RRDRV = 0 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER FET 
td(on)(Idrain) Drain current turn-on delay time From VIN > VIN,IT+ to ID > 50 mA, VBUS = 400 V, LHB current = 2 A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 75 ns
slew rate setting 1 34
slew rate setting 2 28
slew rate setting 3 (fastest) 23
td(on) Turn-on delay time From VIN > VIN,IT+ to VDS < 320 V, VBUS = 400 V, LHB current = 2 A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 107 ns
slew rate setting 1 47
slew rate setting 2 37
slew rate setting 3 (fastest) 28
td(off) Turn-off delay time From VIN < VIN,IT– to VDS > 80 V, VBUS = 400 V, LHB current = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters 33 ns
tf(off) Turn-off fall time From VDS > 80 V to VDS > 320 V, VBUS = 400 V, LHB current = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters 21 ns
Turn-on slew rate From VDS < 250 V to VDS < 150 V, TJ = 25℃, VBUS = 400 V, LHB current = 2 A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 17 V/ns
slew rate setting 1 42
slew rate setting 2 65
slew rate setting 3 (fastest) 125