Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware that the nameplate drain-source voltage cannot be used as an equivalent point to compare devices across technologies. The nameplate drain-source voltage of a silicon FET is set by the avalanche breakdown voltage. The nameplate drain-source voltage of a GaN FET is set by the long term compliance to data sheet specifications.

Exceeding the nameplate drain-source voltage of a silicon FET can lead to immediate and permanent damage. Meanwhile, the breakdown voltage of a GaN FET is much higher than the nameplate drain-source voltage. For example, the breakdown drain-source voltage of the LMG3624 GaN power FET is more than 800V which allows the LMG3624 to operate at conditions beyond an identically nameplate rated silicon FET.

The LMG3624 GaN power FET switching capability is explained with the assistance of Figure 7-1. The figure shows the drain-source voltage versus time for the LMG3624 GaN power FET for two distinct switch cycles in a switching application. No claim is made about the switching frequency or duty cycle. The LMG3624 GaN power FETs are intended to be turned on in either zero-voltage switching (ZVS) or discontinuous-conduction mode (DCM) switching conditions.

Figure 7-1 GaN Power FET Switching Capability

Each cycle starts before t₀ with the FET in the on state. At t₀ the GaN FET turns off and parasitic elements cause the drain-source voltage to ring at a high frequency. The high frequency ringing has damped out by t₁. Between t₁ and t₂ the FET drain-source voltage is set by the characteristic response of the switching application. The characteristic is shown as a flat line (plateau), but other responses are possible. At t₂ the GaN FET turns on. For rare surge events, the transient ring voltage is limited to 800V and the plateau voltage is limited to 720V.