SLUSFB7A September   2023  – June 2024 LMG3624

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Turn-On Slew-Rate Control
      3. 7.3.3 Current-Sense Emulation
      4. 7.3.4 Input Control Pins (EN, IN)
      5. 7.3.5 AUX Supply Pin
        1. 7.3.5.1 AUX Power-On Reset
        2. 7.3.5.2 AUX Under-Voltage Lockout (UVLO)
      6. 7.3.6 Overcurrent Protection
      7. 7.3.7 Overtemperature Protection
      8. 7.3.8 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Turn-On Slew-Rate Design
        2. 8.2.2.2 Current-Sense Design
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REQ|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

1) Symbol definitions: ID = D to S current;  IS = S to D current; ICS(src) = current out of CS;  2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; VDS = 520V; 10V ≤ VAUX ≤ 26V; VEN = 5V; VIN = 0V; RRDRV = 0Ω; RCS = 100Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER FET 
RDS(on) Drain-source (D to S) on resistance  VIN = 5V, ID = 3A, TJ = 25°C 170 mΩ
VIN = 5V, ID = 3A, TJ = 125°C 303
IDSS Drain (D to S) leakage current VDS = 650V, TJ = 25°C 2 µA
VDS = 650V, TJ = 125°C 10
QOSS Output (D to S) charge VDS = 400V 20.0 nC
COSS Output (D to S) capacitance 29 pF
EOSS Output (D to S) capacitance stored energy 2.69 µJ
COSS,er Energy related effective output (D to S) capacitance 33.3 pF
COSS,tr Time related effective output (D to S) capacitance VDS = 0V to 400V 49.3 pF
QRR Reverse recovery charge 0 nC
OVERCURRENT PROTECTION
IT(OC) Overcurrent fault – threshold current 5.4 6 6.6 A
CS
Current sense gain (ICS(src) / ID) VIN = 5V, 0V ≤ VCS ≤ 2V, 0A ≤ ID < IT(OC) 0.965 mA/A
Current sense input offset current VIN = 5V, 0V ≤ VCS ≤ 2V, 0A ≤ ID < IT(OC) –55 55 mA
Initial held output after overcurrent fault occurs while IN remains high VIN = 5V, 0V ≤ VCS ≤ 2V 7 mA
ICS(src)(OC)(final) Final held output after overcurrent fault occurs while IN remains high VIN = 5V, 0V ≤ VCS ≤ 2V 10 12 15.5 mA
Output clamp voltage VIN = 5V, ID = 5.2A, CS sinking 5mA from external source 2.55 V
EN, IN
VIT+ Positive-going input threshold voltage 1.7 2.45 V
VIT– Negative-going input threshold voltage 0.7 1.3 V
Input threshold voltage hysteresis 1 V
Pull-down input resistance 0V ≤ VPIN ≤ 3V 200 400 600 kΩ
Pull-down input current 10V ≤ VPIN ≤ 26V; VAUX = 26V 10 µA
OVERTEMPERATURE PROTECTION
Temperature fault – postive-going threshold temperature 165 °C
Temperature fault – negative-going threshold temperature 145 °C
Temperature fault – threshold temperature hysteresis 20 °C
FLT
Low-level output voltage FLT sinking 1mA while asserted 200 mV
Off-state sink current VFLT = VAUX while de-asserted 1 µA
AUX
VAUX,T+(UVLO) UVLO – positive-going threshold voltage 8.9 9.3 9.7 V
UVLO – negative-going threshold voltage 8.6 9.0 9.4 V
UVLO – threshold voltage hysteresis 250 mV
Standby quiescent current VEN = 0V 50 80 µA
Quiescent current 240 360 µA
Operating current VIN = 0V or 5V, VDS = 0V, ID = 0A, fIN = 500kHz 2.0 mA