SNOSDL9A December   2024  – December 2025 LMG5126

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Multi Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSA, CSB)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSA, CSB)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 GAN Drivers, Integrated Boot Capacitor and Diode, and Hiccup Mode Fault Protection
      17. 6.3.17 Signal Deglitch Overview
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Custom Design With WEBENCH® Tools
        2. 7.2.3.2  Determine the Total Phase Number
        3. 7.2.3.3  Determining the Duty Cycle
        4. 7.2.3.4  Timing Resistor RT
        5. 7.2.3.5  Inductor Selection Lm
        6. 7.2.3.6  Current Sense Resisitor Rcs
        7. 7.2.3.7  Current Sense Filter RCSFA, RCSFB, CCS
        8. 7.2.3.8  Snubber Components
        9. 7.2.3.9  Vout Programming
        10. 7.2.3.10 Input Current Limit (ILIM/IMON)
        11. 7.2.3.11 Minimum Load Resistor
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 Output Capacitor Cout
        15. 7.2.3.15 Input Capacitor Cin
        16. 7.2.3.16 VCC Capacitor CVCC
        17. 7.2.3.17 BIAS Capacitor
        18. 7.2.3.18 VOUT Capacitor
        19. 7.2.3.19 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Note: A top mounted heat sink must be insulative not to short the SW and PGND terminals on the exposed GaN dies.
LMG5126 LMG5126 pin out (top view) Figure 4-1 LMG5126 pin out (top view)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
AGND 1 G Analog ground pin. Connect to the analog ground plane through a wide and short path.
ATRK/DTRK 17 I Output regulation target programming pin. The output voltage regulation target can be programmed by connecting the pin through a resistor to AGND, or by controlling the pin voltage directly with a voltage in the recommended operating range of the pin from 0.2V to 2.0V. A digital PWM signal between 8% to 80% duty cycle sets the output voltage regulation in the recommended operating range.
BIAS 6 P Supply voltage input to the VCC regulator. Connect a 1μF local BIAS capacitor from the pin to ground.
CFG1 11 I

Device configuration pin. Sets the Spread Spectrum mode, 120% peak current limit latch off, sense voltage and gate drive strength. Connect the pin through a resistor to AGND.
CFG2 10 I

Device configuration pin. Sets if the device is configured as single, primary or secondary device using the internal or external clock and the PGOOD configuration. Connect the pin through a resistor to AGND.
COMP 18 O Output of the internal transconductance error amplifier. Connect the loop compensation components between the pin and AGND.
CSA 4 I Current sense amplifier input. The pin operates as the positive input pin. Input to the internal undervoltage lockout for the input voltage. Connect the pin to the sense resistor.
CSB 5 I Current sense amplifier input. The pin operates as the negative input pin. Connect the pin to the sense resistor.
DLY 16 O Average input current limit delay setting pin. A capacitor from DLY to AGND sets the delay from when VIMON reaches 1.1V until the average input current limit is enabled.
EP 22 G Exposed pad of the package. The Exposed pad must be connected to AGND and soldered to a large ground plane to reduce thermal resistance.
IMON/ILIM 20 O Input current monitor and average input current limit setting pin. Sources a current proportional to the differential current sense voltage. A resistor is connected from this pin to AGND.
MODE 21 I Operation mode selection pin selecting DEM or FPWM. Connect the pin through a resistor to AGND or VCC. The pin can also be connected to a controller.
PGND 8 G Power ground connection pin for low-side FET.
PGOOD 12 O

Power-good indicator with open-drain output stage. The pin is pulled low when the output voltage is less than the undervoltage threshold or greater than the overvoltage threshold based on the CFG2-pin setting. It is also pulled low indicating faults. The pin can be left floating if not used.
RT 15 O Switching frequency setting pin. The switching frequency is programmed by a single resistor between the pin and AGND. The switching frequency is dynamically programmable during operation.
SS 19 O Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. The device forces diode emulation during soft-start time.
SW 7 P Switching node connection.
SYNCIN 13 I External clock synchronization pin. Input for an external clock that overrides the free-running internal oscillator. Connect the SYNCIN pin to ground when SYNCIN is not used.
SYNCOUT 14 O Clock output and OVP as well as ATRK current configuration pin. SYNCOUT provides a phase shifted clock output, set by the CFG2.pin. A resistor is connected to this pin to select the LMG5126OVP level and enable the 20μA ATRK current.
UVLO/EN 3 I Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a resistor divider. If greater than VUVLO-RISING, the device is enabled.
VCC 2 P Output of the internal VCC regulator and supply voltage input of the internal FET drivers. Connect a 4.7μF capacitor between the pin and PGND.
VOUT 9 P Output voltage pin. An internal feedback resistor voltage divider is connected from the pin to AGND.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.