SNOSDL9 December   2024 LMG5126

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Configuration
      2. 6.3.2 Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3 Dual Random Spread Spectrum (DRSS)
      4. 6.3.4 Operation Modes (BYPASS, DEM, FPWM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Determining the Duty Cycle
        2. 7.2.3.2 Timing Resistor RT
        3. 7.2.3.3 Vout Programming
        4. 7.2.3.4 Inductor Selection Lm
        5. 7.2.3.5 Output Capacitor Cout
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
  • VBT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

LMG5126 LMG5126 pin out (top view) Figure 4-1 LMG5126 pin out (top view)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
AGND1GAnalog ground pin. Connect to the analog ground plane through a wide and short path.
VCC2POutput of the internal VCC regulator and supply voltage input of the internal FET drivers. Connect a 4.7μF capacitor between the pin and GND.
UVLO/EN 3 I Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a resistor divider. If greater than VUVLO-RISING, the device is enabled.
CSA 4 I Current sense amplifier input. The pin operates as the positive input pin. Input to the internal undervoltage lockout for the input voltage.
CSB 5 I Current sense amplifier input. The pin operates as the negative input pin.
BIAS 6 P Supply voltage input to the VCC regulator. Connect a 1μF local BIAS capacitor from the pin to ground.
SW 7 P Switching node connection.
GND 8 G Power ground connection pin for low-side FET.
VOUT 9 P Output voltage pin. An internal feedback resistor voltage divider is connected from the pin to AGND.
CFG2 10 I

Device configuration pin. Sets if the device is configured as single, primary or secondary device using the internal or external clock and the PGOOD configuration.
CFG1 11 I

Device configuration pin. Sets the Spread Spectrum mode, 120% peak current limit latch off, sense voltage and gate drive strength.
PGOOD 12 O

Power-good indicator with open-drain output stage. The pin is pulled low when the output voltage is less than the undervoltage threshold or greater than the overvoltage threshold based on the CFG2-pin setting. It is also pulled low indicating faults. The pin can be left floating if not used.
SYNCIN 13 I External clock synchronization pin. Input for an external clock that overrides the free-running internal oscillator. Connect the SYNCIN pin to ground when it is not used.
SYNCOUT 14 O Clock output and OVP as well as ATRK current configuration pin. SYNCOUT provides a phase shifted clock output, set by the CFG2.pin. A resistor is connected to this pin to select the LMG5126OVP level and enable the 20μA ATRK current.
RT 15 O Switching frequency setting pin. The switching frequency is programmed by a single resistor between the pin and AGND. Switching frequency is dynamically programmable during operation.
DLY 16 O Average input current limit delay setting pin. A capacitor from DLY to AGND sets the delay from when VIMON reaches 1V until the average input current limit is enabled.
ATRK/DTRK 17 I Output regulation target programming pin. The output voltage regulation target can be programmed by connecting the pin through a resistor to AGND, or by controlling the pin voltage directly with a voltage in the recommended operating range of the pin from 0.2V to 2.0V. A digital PWM signal between 8% to 80% duty cycle sets the output voltage regulation in the recommended operating range.
COMP 18 O Output of the internal transconductance error amplifier. Connect the loop compensation components between the pin and AGND.
SS 19 O Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. The device forces diode emulation during soft-start time.
IMON/ILIM 20 O Input current monitor and average input current limit setting pin. Sources a current proportional to the differential current sense voltage. A resistor is connected from this pin to AGND.
MODE 21 I Operation mode selection pin selecting DEM or FPWM.
EP 22 G Exposed pad of the package. The Exposed pad must be connected to AGND and soldered to a large ground plane to reduce thermal resistance.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.