SNOSDL9 December   2024 LMG5126

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Configuration
      2. 6.3.2 Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3 Dual Random Spread Spectrum (DRSS)
      4. 6.3.4 Operation Modes (BYPASS, DEM, FPWM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Determining the Duty Cycle
        2. 7.2.3.2 Timing Resistor RT
        3. 7.2.3.3 Vout Programming
        4. 7.2.3.4 Inductor Selection Lm
        5. 7.2.3.5 Output Capacitor Cout
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
  • VBT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.1 Shutdown State

The device shuts down for UVLO/EN pin = low consuming 2μA from the BIAS pin and 48μA from the pins connected to VI. In shutdown, COMP, SS, and PGOOD are grounded. The VCC regulator is disabled.