SNOSDL9 December   2024 LMG5126

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Configuration
      2. 6.3.2 Switching Frequency and Synchronization (SYNCIN)
      3. 6.3.3 Dual Random Spread Spectrum (DRSS)
      4. 6.3.4 Operation Modes (BYPASS, DEM, FPWM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Determining the Duty Cycle
        2. 7.2.3.2 Timing Resistor RT
        3. 7.2.3.3 Vout Programming
        4. 7.2.3.4 Inductor Selection Lm
        5. 7.2.3.5 Output Capacitor Cout
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
  • VBT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Typical values correspond to TJ = 25 °C. Minimum and maximum limits apply over TJ = -40 °C to 150 °C. Unless otherwise stated, VI = VBIAS = 12 V, VOUT = 24 V, fSW = 400 kHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT (BIAS, VCC)
ISD VI current in shutdown state (BIAS connected to VI). Current into BIAS, CSA, CSB, SW. VUVLO/EN = 0V, VOUT = 12V, TJ = –40°C to 85°C 50 200 µA
ISD_BIAS BIAS-pin current in shutdown state. VUVLO/EN = 0V, VOUT = 12V, TJ = –40°C to 85°C 2 5 µA
ISD_VOUT VOUT-pin current in shutdown state. VUVLO/EN = 0V, VOUT = 12V, TJ = –40°C to 85°C 0.001 0.5 µA
IQ_BIAS_FPWM BIAS-pin quiescent current in active state, FPWM-Mode, internal clock (not-switching, RT and IMON current is excluded). VUVLO/EN = 2.0V, CFG1 = level 10, CFG2 = level 1, VATRK = 0.8V, no load, TJ = –40°C to 125°C 1.1 2.5 mA
IQ_BIAS_DEM BIAS-pin quiescent current  in active state, DEM-Mode, internal clock (not-switching, RT and IMON current is excluded). VUVLO/EN = 2.0V, CFG1 = level 10, CFG2 = level 1, VATRK = 0.8V, no load, TJ = –40°C to 125°C 1.2 2 mA
IQ_VOUT_FPWM VOUT-pin quiescent current in active state, FPWM-Mode, internal clock (not-switching). VUVLO/EN = 2.0V, CFG1 = level 10, CFG2 = level 1, VATRK = 0.8V, no load, TJ = –40°C to 125°C 250 750 µA
IQ_BIAS_BYP BIAS-pin current in bypass state (RT and IMON current is excluded). VUVLO/EN = 2.0V, CFG1 = level 10, CFG2 = level 1, VOUT = 12V, TJ = –40°C to 125°C 1.5 8.5 mA
IBIAS BIAS-pin bias current when VCC is supplied by BIAS,  FPWM-Mode (not-switching, RT and IMON current is excluded). VBIAS = 12V, IVCC = 100mA 100 110 mA
IVOUT VOUT-pin bias current when VCC is supplied by VOUT,  FPWM-Mode (not-switching). VBIAS = 3.3V, IVCC = 100mA 100 110 mA
VCC REGULLATOR (VCC)
VBIAS-RISING Threshold to switch VCC supply from VOUT-pin to BIAS-pin VBIAS rising 6.0 6.25 6.5 V
VBIAS-FALLING Threshold to switch VCC supply from BIAS-pin to VOUT-pin VBIAS falling 5.6 5.9 6.2 V
VBIAS-HYS VCC supply threshold hysteresis 250 350 mV
VVCC-REG1 VCC regulation No load 5.1 5.3 5.5 V
VVCC-REG2 VCC regulation during dropout VBIAS = 5.9V, IVCC = 100mA 4.5 5.2 V
VVCC-UVLO-RISING VCC UVLO threshold VCC rising 4.1 4.2 4.3 V
VVCC-UVLO-FALLING VCC UVLO threshold VCC falling 3.8 3.9 4.0 V
VVCC-UVLO-HYS VCC UVLO threshold hysteresis VCC falling 300 mV
IVCC-CL VCC sourcing current limit VVCC = 4V 100 mA
ENABLE (EN/UVLO)
VEN-RISING Enable threshold EN rising 0.50 0.55 0.6 V
VEN-FALLING Enable threshold EN falling 0.40 0.45 0.50 V
VEN-HYS Enable hysteresis EN falling 100 mV
REN EN pulldown resistance VEN = 0.2V 30 37 50 kΩ
VUVLO-RISING UVLO threshold UVLO rising 1.05 1.1 1.15 V
VUVLO-FALLING UVLO threshold UVLO falling 1.025 1.075 1.125 V
VUVLO-HYS UVLO hysteresis UVLO falling 25 mV
CONFIGURATION (CFG1, CFG2, SYNCOUT)
RCFGx_1 CFGx level 1 resistance 0 0.1 kΩ
RCFGx_2 CFGx level 2 resistance 0.48 0.51 0.54 kΩ
RCFGx_3 CFGx level 3 resistance 1 1.15 1.3 kΩ
RCFGx_4 CFGx level 4 resistance 1.81 1.9 2.00 kΩ
RCFGx_5 CFGx level 5 resistance 2.57 2.7 2.84 kΩ
RCFGx_6 CFGx level 6 resistance 3.61 3.8 3.99 kΩ
RCFGx_7 CFGx level 7 resistance 4.85 5.1 5.36 kΩ
RCFGx_8 CFGx level 8 resistance 6.18 6.5 6.83 kΩ
RCFGx_9 CFGx level 9 resistance 7.89 8.3 8.72 kΩ
RCFGx_10 CFGx level 10 resistance 9.98 10.5 11.03 kΩ
RCFGx_11 CFGx level 11 resistance 12.64 13.3 13.97 kΩ
RCFGx_12 CFGx level 12 resistance 15.39 16.2 17.01 kΩ
RCFGx_13 CFGx level 13 resistance 19.48 20.5 21.53 kΩ
RCFGx_14 CFGx level 14 resistance 23.66 24.9 26.15 kΩ
RCFGx_15 CFGx level 15 resistance 28.60 30.1 31.61 kΩ
RCFGx_16 CFGx level 16 resistance 34.68 36.5 100 kΩ
RSYNCOUT_1 SYNCOUT level 1 resistance 0 24.9 26.15 kΩ
RSYNCOUT_2 SYNCOUT level 2 resistance 29.94 31.5 33.09 kΩ
RSYNCOUT_3 SYNCOUT level 3 resistance 37.92 39.9 41.91 kΩ
RSYNCOUT_4 SYNCOUT level 4 resistance 46.17 48.6 51.03 kΩ
RSYNCOUT_5 SYNCOUT level 5 resistance 58.44 61.5 64.59 kΩ
RSYNCOUT_6 SYNCOUT level 6 resistance 70.98 75 78.45 kΩ
RSYNCOUT_7 SYNCOUT level 7 resistance 85.8 90.9 94.83 kΩ
RSYNCOUT_8 SYNCOUT level 8 resistance 104.04 110 200 kΩ
SWITCHING FREQUENCY
VRT RT regulation 0.7 0.75 0.8 V
fSW1 Switching frequency fSW = 300kHz, RT = 104.4kΩ 255 300 345 kHz
fSW2 Switching frequency fSW = 2500kHz, RT = 12kΩ 2250 2500 2750 kHz
tON-MIN Minimum controllable on-time fSW = 2200kHz 14 20 50 ns
tOFF-MIN Minimum forced off-time fSW = 2200kHz 45 65 85 ns
DMAX1 Maximum duty cycle limit  fSW = 300kHz 97% 98% 99%
DMAX2 Maximum duty cycle limit  fSW = 2200kHz 81% 86% 91%
SYNCHRONIZATION (SYNCIN, SYNCOUT)
SYNCIN frequency acitivity detection threshold Spread Spectrum = off 0 50 kHz
SYNCIN activity detection cycles 3 cycles
fSYNC Syncing frequency range from RT set frequency during synchronization. single device Frequency synchronized to ext. clock min. = 300kHz, max. = 2500kHz. –50% 50%
multi device –25% 25%
VSYNCIN_H SYNCIN high level input voltage SYNCIN rising 1.19 5.25 V
VSYNCIN_L SYNCIN low level input voltage SYNCIN falling –0.3 0.41 V
Minimum SYNCIN pullup / pulldown pulse width 60 ns
VOUT PROGRAMMING (ATRK/DTRK)
VOUT_REG VOUT regulation with ATRK voltage ATRK = 0.2V 5.88 6 6.12 V
ATRK = 0.4V 11.82 12 12.18 V
ATRK = 0.8V 23.64 24 24.36 V
ATRK = 1.6V 47.28 48 48.72 V
ATRK = 2V 59.10 60 60.90 V
GDTRK Conversion ratio of DTRK duty cycle to VATRK fDTRK = 100kHz, 2200kHz 25 mV / %
DTRK duty cycle range 8% 80%
VATRK ATRK voltage for given DTRK duty cycle fDTRK = 100kHz, DC = 8% 0.196 0.2 0.204 V
fDTRK = 100kHz, DC = 40% 0.99 1 1.01 V
fDTRK = 100kHz, DC = 80% 1.98 2 2.02 V
fDTRK = 440kHz, DC = 8% 0.196 0.2 0.204 V
fDTRK = 440kHz, DC = 40% 0.99 1 1.01 V
fDTRK = 440kHz, DC = 80% 1.98 2 2.02 V
fDTRK = 2200kHz, DC = 8% 0.19 0.2 0.21 V
fDTRK = 2200kHz, DC = 40% 0.98 1 1.02 V
fDTRK = 2200kHz, DC = 80% 1.98 2 2.02 V
IATRK Source current when activated through resistor setting at SYNCOUT 19.8 20 20.2 µA
VDTRK_H DTRK high level input voltage DTRK rising 1.19 5.25 V
VDTRK_L DTRK low level input voltage DTRK falling -0.3 0.41 V
Minimum DTRK pull-up / pull-down pulse width 25 ns
SOFT START (SS)
ISS Soft-start current 42.5 50 57.5 µA
VSS-DONE Soft-start done threshold 2.15 2.2 2.25 V
RSS SS pulldown switch RDSON 30 70 Ω
VSS-DIS SS discharge detection threshold 20 45 70 mV
CURRENT SENSE (CSA, CSB)
ACS Current sense amplifier gain 10 V/V
VCLTH Positive peak current limit threshold 60mV sensing Referenced to CS input 54 60 66 mV
30mV sensing 24 30 36 mV
VNCLTH Negative peak current limit threshold 60mV and 30mV sensing Referenced to CS input, FPWM mode –33 –30 –27 mV
VICL Input current limit 60mV sensing Referenced to CS input 65 72 80 mV
30mV sensing 32.4 36 39.6 mV
Peak current limit trip delay 50 ns
VZCD ZCD threshold (CSA–CSB) CS input falling, DEM 0 1 2 mV
VZCD_BYP ZCD threshold in bypass mode (CSA–CSB). –3 –1.5 0 mV
VSLOPE Peak slope compensation amplitude Referenced to CS input, fSW = 300kHz 40 48 55 mV
ICSA CSA current Device in Standby state, VI = VBIAS = VOUT = 12V 150 170 µA
ICSB CSB current 1.2 µA
CURRENT MONITOR / LIMITER WITH DELAY (IMON/ILIM)
GIMON Transconductance Gain 0.283 0.333 0.383 μA/mV
IOFFSET Offset current 3 4 5 μA
VILIM ILIM regulation target 0.93 1 1.07 V
VILIM_th ILIM activation threshold 1 V
VILIM_reset DLY reset threshold ILIM falling, referenced to VILIM 87% 90% 93%
IDLY DLY sourcing/sinking current 5 μA
VDLY_peak_rise VDLY rising 2.6 V
VDLY_peak_fall VDLY falling 2.4 V
VDLY_valley 0.2 V
OPERATION MODES
VMODE_H MODE-pin high level FPWM 1.19 5.25 V
VMODE_L MODE-pin low level DEM –0.3 0.41 V
OVER / UNDER VOLTAGE MONITOR
VOVP-H Overvoltage threshold rising VOUT rising (referenced to error amplifier reference) 108% 110% 112%
VOVP-L Overvoltage threshold falling VOUT falling (referenced to error amplifier reference) 101% 103% 105%
VOVP_max-H Max. overvoltage threshold rising 25V setting VOUT rising (referenced to error amplifier reference) 23 24 25 V
35V setting 33 34 35 V
50V setting 48 49 50 V
65V setting 63 64 65 V
VOVP_max-L Max. overvoltage threshold rising 25V setting VOUT falling (referenced to error amplifier reference) 22 23 24 V
35V setting 32 33 34 V
50V setting 47 48 49 V
65V setting 62 63 64 V
VUVP-H Undervoltage threshold VOUT rising (referenced to error amplifier reference) 91% 93% 95%
VUVP-L Undervoltage threshold VOUT falling (referenced to error amplifier reference) 88% 90% 92%
PGOOD
RPGOOD PGOOD pull-down switch RDSON 1mA sinking 90 180 Ω
Minimum BIAS for valid PGOOD 2 V
THERMAL SHUTDOWN (TSD)
TTSD-RISING Thermal shutdown threshold Temperature rising 175 °C
TTSD-HYS Thermal shutdown hysteresis 15 °C
TIMINGS
STANDBYtimer STANDBY timer 130 150 170 µs