SNLS285 Data sheet

SNLS285H April 2008 – May 2016 LMH0303

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RUM|16
- MPQF223A

Thermal pad, mechanical data (Package|Pins)

RUM|16
- QFND453A

Orderable Information

7 Detailed Description

7.1 Overview

The LMH0303 ST 424, ST292, ST259 serial digital cable driver is a monolithic, high-speed cable driver designed for use in serial digital video data transmission applications. The LMH0303 drives 75-Ω transmission lines (Belden 8281, 1694A, Canare L-5CFB, or equivalent) at data rates up to 2.97 Gbps.

The LMH0303 provides two selectable slew rates for ST 259 and ST 292/424 compliance. The output voltage swing is adjustable through a single external resistor ( R_REF) or SMBus interface in 5-mV steps.

The LMH0303 cable detect feature senses near-end termination to determine if a cable is attached to the output BNC. The LMH0303 input loss of signal (LOS) detects the presence of a valid signal at the 100-Ω differential input of the cable driver. These features can be used to activate power-save mode. These features are accessible through an SMBus interface.

The LMH0303 is powered from a single 3.3 V supply. Power consumption is typically 130 mW in SD mode and 155 mW in HD mode. The LMH0303 is available in a 16-pin WQFN package.

7.2 Functional Block Diagram

7.3 Feature Description

The LMH0303 data path consists of several key blocks as shown in the Functional Block Diagram. These key circuits are:

Loss-of-signal detector
Input interfacing
Output interfacing
Output slew rate control
Cable fault detection
SMBus configuration

7.3.1 Loss-of-Signal Detector

The LMH0303 detects when the input signal does not have a video-like pattern. Self-oscillation and low levels of noise are rejected. This loss-of-signal detector allows a very sensitive input stage that is robust against coupled noise without any degradation of jitter performance. Through the SMBus, the loss-of-signal detector can either add an input offset or mute the outputs. An offset is added by default. Additionally, the loss-of-signal detector can be linked to the ENABLE functionality so that when the LOS goes low, ENABLE also goes low.

7.3.2 Input Interfacing

The LMH0303 accepts either differential or single-ended input. For single-ended operation, the unused input must be properly terminated.

7.3.3 Output Interfacing

The LMH0303 uses current mode outputs. Single-ended output levels are 800 mV_P-P into 75-Ω AC-coupled coaxial cable with an R_REF resistor value of 750 Ω. The R_REF resistor is connected between the R_REF pin and V_CC.

The R_REF resistor should be placed as close as possible to the R_REF pin. In addition, the copper in the plane layers below the R_REF network should be removed to minimize parasitic capacitance.

7.3.4 Output Slew Rate Control

The LMH0303 output rise and fall times are selectable for either ST259 or ST 424 or 292 compliance through the SD/HD pin. For slower rise and fall times, or ST 259 compliance, SD/HD is set high. For faster rise and fall times, or ST 424 and ST 292 compliance, SD/HD is set low. SD/HD may also be controlled using the SMBus, provided the SD/HD pin is held low. SD/HD has an internal pulldown.

7.3.5 Cable Fault Detection

The LMH0303 termination fault detection purpose is to provide an indication when no cable is connected to the output (near end). The termination fault detection works by detecting reflections on the output. The device measures the peak-to-peak output voltage. The output amplitude is normally 800 mV_p-p. No termination results in 2x the output voltage (1600 mV_p-p) due to the 100% reflection.

When a video signal (or AC test signal) is present on SDI, the device senses the SDO and SDO amplitudes. If the output is not properly terminated (through a terminated cable or local termination), the amplitude will be higher than expected, and the termination fault signal is asserted. The termination fault signal is deasserted when the proper termination is applied. This feature allows the system designer the flexibility to react to cable attachment and removal. Note that a long length of cable will look like a proper termination at the device output. The cable driver must be enabled for the termination detection to operate. If the termination fault will be used to power down the LMH0303, then periodic polling (enabling) is recommended to monitor the output termination. For example, when a fault condition is triggered, ENABLE can be driven low to power down the device. The LMH0303 should be re-enabled periodically to check the status of the output termination. The LMH0303 must be powered on for at least 4 ms for termination fault detection to work.

7.3.6 SMBus Interface

The System Management Bus (SMBus) is a two-wire interface designed for the communication between various system component chips. By accessing the control functions of the circuit through the SMBus, pin count is kept to a minimum while allowing a maximum amount of versatility. The LMH0303 has several internal configuration registers which may be accessed through the SMBus.

The 7-bit default address for the LMH0303 is 0x17. The LSB is set to 0'b for a WRITE and 1'b for a READ, so the 8-bit default address for a WRITE is 0x2E and the 8-bit default address for a READ is 0x2F. The SMBus address may be dynamically changed.

In applications where there might be several LMH0303s, the SDA, SCL, and FAULT pins can be shared. The SCL, SDA, and FAULT pins are open drain and require external pullup resistors. Multiple LMH0303s may have the FAULT pin wire ORed. This signal becomes active when either loss of signal is detected or any termination faults are detected. The registers may be read in order to determine the cause. Additionally, each signal can be masked from the FAULT pin.

7.3.6.1 Transfer of Data through the SMBus

During normal operation the data on SDA must be stable during the time when SCL is High.

There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.

STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.

IDLE: If SCL and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for t_HIGH, then the bus will transfer to the IDLE state.

7.3.6.2 SMBus Transactions

The device supports WRITE and READ transactions. See Table 1 for register address, type (Read/Write, Read Only), default value, and function information.

7.3.6.2.1 Writing a Register

To write a register, the following protocol is used (see SMBus 2.0 specification).

The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
The Device (Slave) drives the ACK bit (0).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (0).
The Host drives the 8-bit data byte.
The Device drives an ACK bit (0).
The Host drives a STOP condition.

The WRITE transaction is completed, the bus goes IDLE, and communication with other SMBus devices may now occur.

7.3.6.2.2 Reading a Register

To read a register, the following protocol is used (see SMBus 2.0 specification).

The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
The Device (Slave) drives the ACK bit (0).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (0).
The Host drives a START condition.
The Host drives the 7-bit SMBus Address, and a 1 indicating a READ.
The Device drives an ACK bit 0.
The Device drives the 8-bit data value (register contents).
The Host drives a NACK bit 1 indicating end of the READ transfer.
The Host drives a STOP condition.

7.3.6.3 Communicating With Multiple LMH0303 Cable Drivers through the SMBus

A common application for the LMH0303 uses multiple cable driver devices. Even though the LMH0303 devices all have the same default SMBus device ID (address), it is still possible for them share the SMBus signals as shown in Figure 4. A third signal is required from the host to the first device. This signal acts as a Enable or Reset signal. Additional LMH0303s are controlled from the upstream device. In this control scheme, multiple LMH0303s may be controlled through the two-wire SMBus and the use of one General Purpose Output (GPO) signal. Other SMBus devices may also be connected to the two wires, assuming they have their own unique SMBus addresses.

Figure 4. SMBus Configuration for Multiple LMH0303 Cable Drivers

The RSTI pin of the first device is controlled by the system with a GPO pin from the host. The first LMH0303 RSTO pin is then daisy chained to the next device's RSTI pin. That device’s RSTO pin is connected to the next device and so on.

The procedure at initialization is to:

Hold the host GPO pin Low in RESET, to the first device. RSTO output default is also Low which holds the next device in RESET in the chain.
Raise the host GPO signal to LMH0303 #1 RSTI input pin.
Write to Address 0x2E Register 0 with the new address value (for example 0x2C).
Upon writing Register 0 in LMH0303 #1, its RSTO signal will switch High. Its new address is 0x2C, and the next LMH0303 in the chain will now respond to the default address of 0x2E.
The process is repeated until all LMH0303 devices have a unique address loaded.
Direct SMBus writes and reads may now take place between the host and any addressed device.

The 7-bit address field allows for 128 unique addresses. The above procedure allows for the reprogramming of the LMH0303 devices such that multiple devices may share the two-wire SMBus. Make sure all devices on the bus have unique device IDs.

If power is toggled to the system, the SMBus address routine needs to be repeated.

7.4 Device Functional Modes

The LMH0303 features can be controlled through the pin or SMBus interface. SMBus Interface describes detailed operation using SMBus interface.

7.5 Register Maps

Table 1 lists the SMBus registers of the LMH0303 device.

Table 1. SMBus Registers

ADDRESS	R/W	NAME	BITS	FIELD	DEFAULT	DESCRIPTION
0x00	R/W	ID	7:1	DEVID	0010111	Device ID. Writing this register will force the RSTO pin high. Further access to the device must use this 7-bit address.
0x00	R/W	ID	0	RSVD	0	Reserved as 0. Always write 0 to this bit.
0x01	R	STATUS	7:3	RSVD	00000	Reserved.
			2	TFN	0	Termination Fault for SDI. 0: No Termination Fault Detected. 1: Termination Fault Detected.
			1	TFP	0	Termination Fault for SDI. 0: No Termination Fault Detected. 1: Termination Fault Detected.
			0	LOS	0	Loss Of Signal (LOS) detect at input. 0: No Signal Detected. 1: Signal Detected.
0x02	R/W	MASK	7	SD	0	SD Rate select bit. If the SD/HD pin is set to V_CC, it overrides this bit. With the SD/HD pin set to ground, this bit selects the output edge rate as follows: 0: HD edge rate. 1: SD edge rate.
			6	RSVD	0	Reserved as 0. Always write 0 to this bit.
			5	PD	0	Power Down for SDO output stage. If the ENABLE pin is set to ground, it overrides this bit. With the ENABLE pin set to V_CC, PD functions as follows: 0: SDO active. 1: SDO powered down.
			4:3	RSVD	00	Reserved as 00. Always write 00 to these bits.
			2	MTFN	0	Mask TFN from affecting FAULT pin. 0: TFN=1 will cause FAULT to be 0. 1: TFN=1 will not affect FAULT; the condition is masked off.
			1	MTFP	0	Mask TFP from affecting FAULT pin. 0: TFP=1 will cause FAULT to be 0. 1: TFP=1 will not affect FAULT; the condition is masked off.
			0	MLOS	0	Mask LOS from affecting FAULT pin. 0: LOS=0 will cause FAULT to be 0. 1: LOS=0 will not affect FAULT; the condition is masked off.
0x03	R/W	DIRECTION	7	HDTFThreshLSB	1	Least Significant Bit for HDTFThresh detection threshold. Combines with HDTFThresh bits in register 0x04.
			6	SDTFThreshLSB	1	Least Significant Bit for SDTFThresh detection threshold. Combines with SDTFThresh bits in register 0x05.
			5:3	RSVD	000	Reserved as 000. Always write 000 to these bits.
			2	DTFN	0	Direction of TFN that affects FAULT pin (when not masked). 0: TFN=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TFN=0 will cause FAULT to be 0 (when the condition is not masked off).
			1	DTFP	0	Direction of TFP that affects FAULT pin (when not masked). 0: TFP=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TFP=0 will cause FAULT to be 0 (when the condition is not masked off).
			0	DLOS	0	Direction of LOS that affects FAULT pin (when not masked). 0: LOS=0 will cause FAULT to be 0 (when the condition is not masked off). 1: LOS=1 will cause FAULT to be 0 (when the condition is not masked off).
0x04	R/W	OUTPUT	7:5	HDTFThresh	100	Sets the Termination Fault threshold for SDO, when SD is set to HD rates (0). Combines with HDTFThreshLSB in register 0x03 (default for combined value is 1001).
0x04	R/W	OUTPUT	4:0	AMP	10000	SDO output amplitude in roughly 5 mV steps.
0x05	R/W	OUTPUTCTRL	7	RSVD	0	Reserved as 0. Always write 0 to this bit.
			6	FLOSOF	0	Force LOS to always OFF in regards to its effect on the output signal. This forces the device into either the mute or “add offset” state. The LOS bit in register 0x01 still reflects the correct state of LOS. 0: LOS operates normally, muting or adding offset as specified by the MUTE bit. 1: Muting or adding offset is always in place as specified by the MUTE bit.
			5	FLOSON	0	Force LOS to always ON in regards to its effect on the output signal. This prevents the device from muting or adding offset. The LOS bit in register 0x01 still reflects the correct state of LOS. 0: LOS operates normally, muting or adding offset as specified in the MUTE bit. 1: Muting or adding offset never occurs.
			4	LOSEN	0	Configures LOS to be combined with the ENABLE functionality. 0: Only the PD bit and ENABLE pin affect the power down state of the output drivers. 1: If the ENABLE pin is set to ground, it powers down the output drivers regardless of the state of LOS or the PD bit. With the ENABLE pin set to V_CC, LOS=0 will power down the output drivers, and LOS=1 will leave the power down state dependent on the PD bit.
			3	MUTE	0	Selects whether the device will MUTE when loss of signal is detected or add an offset to prevent self oscillation. When an input signal is detected (LOS=1), the device will operate normally. 0: Loss of signal will force a small offset to prevent self oscillation. 1: Loss of signal will force the channel to MUTE.
			2:0	SDTFThresh	010	Sets the Termination Fault threshold for SDO, when SD is set to SD rate. Combines with SDTFThreshLSB in register 0x03 (default for combined value is 0101).
0x06	R/W	RSVD	7:0	RSVD	00000000	Reserved as 00000000. Always write 00000000 to these bits.
0x07	R/W	RSVD	7:0	RSVD	00000000	Reserved as 00000000. Always write 00000000 to these bits.
0x08	R/W	TEST	7:5	CMPCMD	000	Compare command. Determines whether the peak value or the current value of the Termination Fault counters is read in registers 0x0A and 0x0B. 000: Resets compare value to 00; registers 0x0A and 0x0B show current counter values. Sets detection to look for MAX peak values. 001: Capture counter 0. Register 0x0A shows peak value. 010: Capture counter 1. Register 0x0B shows peak value. 011, 100: Reserved. 101: Resets compare value to 0x1F. Sets detection to look for MIN peak values. 110, 111: Reserved.
0x08	R/W	TEST	4:0	RSVD	00000	Reserved as 00000. Always write 00000 to these bits.
0x09	R	REV	7:5	RSVD	000	Reserved.
			4:3	DIREV	10	Die Revision.
			2:0	PARTID	011	Part Identifier. Note that single output devices (LMH0303) have the LSB=1. Dual output devices (LMH0307) have the LSB=0.
0x0A	R	TFPCOUNT	7:5	RSVD	000	Reserved.
0x0A	R	TFPCOUNT	4:0	TFPCOUNT	00000	This is either the current value of TFP Counter, or the peak value of the counter, depending on CMPCMD in register 0x08.
0x0B	R	TFNCOUNT	7:5	RSVD	000	Reserved.
0x0B	R	TFNCOUNT	4:0	TFNCOUNT	00000	This is either the current value of TFN Counter, or the peak value of the counter, depending on CMPCMD in register 0x08.