SNLS508 September   2015 LMH0318

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface AC Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Loss of Signal Detector
      2. 8.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 8.3.3 2:1 Multiplexer
      4. 8.3.4 Clock and Data Recovery
      5. 8.3.5 Eye Opening Monitor (EOM)
      6. 8.3.6 Fast EOM
        1. 8.3.6.1 SMBus Fast EOM Operation
        2. 8.3.6.2 SPI Fast EOM Operation
      7. 8.3.7 LMH0318 Device Configuration
        1. 8.3.7.1 MODE_SEL
        2. 8.3.7.2 ENABLE
        3. 8.3.7.3 LOS_INT_N
        4. 8.3.7.4 LOCK
        5. 8.3.7.5 SMBus MODE
        6. 8.3.7.6 SMBus READ/WRITE Transaction
        7. 8.3.7.7 SPI Mode
          1. 8.3.7.7.1 SPI READ/WRITE Transaction
          2. 8.3.7.7.2 SPI Write Transaction Format
          3. 8.3.7.7.3 SPI Read Transaction Format
        8. 8.3.7.8 SPI Daisy Chain
          1. 8.3.7.8.1 SPI Daisy Chain Write Example
          2. 8.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 8.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 8.3.8 Power-On Reset
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Register Maps
      2. 8.5.2 Global Registers
      3. 8.5.3 Receiver Registers
      4. 8.5.4 CDR Registers
      5. 8.5.5 Transmitter Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Guidance for All Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Solder Profile
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

  1. Set trace impedances to 75 Ω ± 5% single ended, 100 Ω ± 5% differential.
  2. Maintain the same signal reference plane for 75 Ω single-end trace, and reference plane for 100 Ω differential traces.
  3. Use the smallest size surface mount components.
  4. Use solid planes. Provide GND or VDD relief under the component pads to minimize parasitic capacitance.
  5. Select trace widths that minimize the impedance mismatch along the signal path.
  6. Select a board stack-up that supports 75 Ω or 50 Ω single-end trace, 100 Ω coupled differential traces.
  7. Use surface mount ceramic capacitors.
  8. Place return loss network as close to the device as possible.
  9. Maintain symmetry on the complimentary signals.
  10. Route 100 Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
  11. Avoid sharp bends; use 45-degree or radial bends.
  12. Walk along the signal path, identify geometry changes and estimate their impedance changes.
  13. Maintain 75 Ω impedance with a well-designed connectors’ footprint.
  14. Consult a 3-D simulation tool to guide layout decisions.
  15. Use the shortest path for VDD and Ground hook-ups; connect pin to planes with vias to minimize or eliminate trace.
  16. When a high speed trace changes layer, provide at least 2 return vias to improve current return path.

11.2 Layout Example

The following example layout demonstrates how the thermal pad should be laid out using standard WQFN board routing guidelines.

LMH0318 layout_example_1.png
Note: Thermal pad is divided into 4 squares with solder paste
Figure 22. LMH0318 Recommended Four Squares Solder Paste
LMH0318 layout_example2.png
5 Vias without solder paste are located between 4 squares solder paste
Figure 23. LMH0318 Recommended Solder Paste Mask and vias
LMH0318 example_layout.png
Top etch plus traces
Figure 24. Example Layout

11.3 Solder Profile

The LMH0318 RTW024A Package solder profile and solder paste material can be found at the following link: SNOA401