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  • LMH0344 3-Gbps HD - SD SDI Adaptive Cable Equalizer

    • SNLS233O April   2007  – July 2015 LMH0344

      PRODUCTION DATA.  

  • CONTENTS
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  • LMH0344 3-Gbps HD - SD SDI Adaptive Cable Equalizer
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Block Description
      2. 7.3.2 Mute Reference (MuteREF)
      3. 7.3.3 Carrier Detect (CD) and Mute
      4. 7.3.4 Input Interfacing
      5. 7.3.5 Output Interfacing
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Dos and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • NYA|25
    • MPBGAD3
  • RUM|16
    • MPQF223A
Thermal pad, mechanical data (Package|Pins)
  • RUM|16
    • QFND453A
Orderable Information
  • snls233o_oa
  • snls233o_pm
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DATA SHEET

LMH0344 3-Gbps HD - SD SDI Adaptive Cable Equalizer

1 Features

  • Compliant With ST 424, ST 292, ST 344, and ST 259(8)
  • Supports DVB-ASI at 270 Mbps
  • Wide Range of Data Rates: 125 Mbps to 2.97 Gbps
  • Equalizes up to 120 Meters of Belden 1694A at 2.97 Gbps, up to 140 Meters of Belden 1694A at 1.485 Gbps, or up to 400 Meters of Belden 1694A at 270 Mbps
  • Equalizes up to 120m of Belden 1694A at 2.97 Gbps With 0.3 UI Maximum Output Jitter
  • Manual Bypass and Output Mute With a Programmable Threshold
  • Single-Ended or Differential Input
  • 50-Ω Differential Outputs (Internal 50-Ω Pullups)
  • Single 3.3-V Supply Operation
  • 280-mW Typical Power Consumption
  • 16-Pin WQFN or 25-Ball CS-BGA Package
  • Industrial Temperature Range: −40°C to +85°C
  • HBM ESD Rating: 8 kV
  • WQFN Version Footprint Compatible With the LMH0044, LMH0384, and LMH0074
  • Replaces the Semtech GS2974A or GS2974B

2 Applications

  • ST 424, ST 292, ST 344, and ST 259 Serial Digital Interfaces(8)
  • Serial Digital Data Equalization and Reception
  • Data Recovery Equalization

3 Description

The LMH0344 3-Gbps HD – SD SDI Adaptive Cable Equalizer is designed to equalize data transmitted over cable (or any media with similar dispersive loss characteristics). The equalizer operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, and ST 259.

The LMH0344 device implements DC restoration to correctly handle pathological data conditions. The equalizer may be driven in either a single-ended or differential configuration.

Additional features include separate carrier detect and output mute pins which may be tied together to mute the output when no signal is present. A programmable mute reference is provided to mute the output at a selectable level of signal degradation.

For applications using the 4:4:4:4 10 bits video format, the LMH0394 cable equalizer will provide better performance.

The device is available in two space–saving packages: a 4-mm × 4-mm 16-pin WQFN and even more space-efficient 3-mm × 3-mm 25-ball CS-BGA package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMH0344 WQFN (16) 4.00 mm × 4.00 mm
CS-BGA (25) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

LMH0344 20199002.gif

4 Revision History

Changes from N Revision (June 2015) to O Revision

  • Fixed typo in Features bullet to change "Equalizes up 120m of Belden 1694A" to "Equalizes up to 120m of Belden 1694A" Go

Changes from M Revision (January 2014) to N Revision

  • Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions; Specifications; Applications and Implementation; Detailed Description; Layout;Device and Documentation Support; Mechanical, Packaging, and Ordering InformationGo
  • Changed "RGBα data patterns" to "4:4:4:4 10-bit video format" in Description sectionGo

Changes from L Revision (April 2013) to M Revision

  • Added BYPASS SentenceGo
  • Added BYPASS SentenceGo

Changes from K Revision (April 2013) to L Revision

  • Changed layout of National Data Sheet to TI formatGo

5 Pin Configurations and Functions

RUM Package
16-Pin WQFN
Top View
LMH0344 20199003.gif
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.

Pin Functions – RUM Package

PIN I/O DESCRIPTION
NAME WQFN
AEC+ 5 I/O, Analog AEC loop filter external capacitor (1-µF) positive connection.
AEC- 6 I/O, Analog AEC loop filter external capacitor (1-µF) negative connection.
BYPASS 7 I, LVCMOS Bypasses equalization and DC restoration when high. No equalization occurs in this mode. This pin does not have an internal pulldown. If the bypass function is not used, this pin requires an external pulldown resistor to disable bypass.
CD 15 O, LVCMOS Carrier detect. CD is high when no signal is present. CD has no function in BYPASS mode.
MUTE 14 I, LVCMOS Output mute. To disable the mute function and enable the output, MUTE must be tied to GND or a low level signal. To force the outputs to a muted state, tie to VCC. CD may be tied to this pin to inhibit the output when no input signal is present. MUTE has no function in BYPASS mode.
MUTEREF 8 I, Analog Mute reference. Sets the threshold for CD and (with CD tied to MUTE) determines the maximum cable to be equalized before muting. MUTEREF may be either unconnected or connected to ground for maximum equalization.
NC — — No connect.
SDI 2 I, Analog Serial data true input.
SDI 3 I,Analog Serial data complement input.
SDO 11 O, Analog Serial data true output.
SDO 10 O, Analog Serial data complement output.
VCC 13 Power Positive power supply (+3.3V).
16
VEE DAP Ground Negative power supply (ground). Note Figure 7 for layout example.
1
4
9
12
NYA Package
25-Ball CS-BGA
Top View
LMH0344 20199006.gif

Pin Functions – NYA Package

PIN I/O DESCRIPTION
NAME CS-BGA BALL
AEC+ E2 I/O, Analog AEC loop filter external capacitor (1-µF) positive connection.
AEC- E3 I/O, Analog AEC loop filter external capacitor (1-µF) negative connection.
BYPASS D3 I, LVCMOS Bypasses equalization and DC restoration when high. No equalization occurs in this mode. This pin does not have an internal pulldown. If the bypass function is not used, this pin requires an external pulldown resistor to disable bypass.
CD A2 O, LVCMOS Carrier detect. CD is high when no signal is present. CD has no function in BYPASS mode.
MUTE B3 I, LVCMOS Output mute. To disable the mute function and enable the output, MUTE must be tied to GND or a low level signal. To force the outputs to a muted state, tie to VCC. CD may be tied to this pin to inhibit the output when no input signal is present. MUTE has no function in BYPASS mode.
MUTEREF E4 I, Analog Mute reference. Sets the threshold for CD and (with CD tied to MUTE) determines the maximum cable to be equalized before muting. MUTEREF may be either unconnected or connected to ground for maximum equalization.
NC A5 — No connect.
B5
C2
C3
C4
D4
E1
SDI C1 I, Analog Serial data true input.
SDI D1 I,Analog Serial data complement input.
SDO C5 O, Analog Serial data true output.
SDO D5 O, Analog Serial data complement output.
VCC A1 Power Positive power supply (+3.3V).
A3
A4
B2
VEE B1 Ground Negative power supply (ground).
B4
D2
E5

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage 4 V
Input voltage (all inputs) −0.3 to VCC+0.3 V
Junction temperature 125 °C
Lead temperature  (soldering 4 seconds) 260 °C
Storage temperature −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±2000
Machine model (MM) 400
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

6.3 Recommended Operating Conditions

MIN TYP MAX UNIT
(VCC – VEE) Supply Voltage 3.135 3.3 3.465 V
Input Coupling Capacitance 1 µF
AEC Capacitor (Connected between AEC+ and AEC-) 1 µF
TA Operating Free Air Temperature −40 25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) LMH0344 UNIT
RUM (WQFN) NYA (CS-BGA)
16 PINS 25 BALL
RθJA Junction-to-ambient thermal resistance 40 58.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 4.5 — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics

over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCMIN Input Common-Mode Voltage 1.9 V
VSDI Input Voltage Swing (SDI, SDI) At LMH0344 input(3)(4) 720 800 950 mVP−P
VCMOUT Output Common-Mode Voltage (SDO, SDO) VCC – VSDO/2 V
VSDO Output Voltage Swing 100-Ω load, differential 750 mVP-P
MUTEREF MUTEREF DC Voltage (floating) 1.3 V
MUTEREF Range 0.6 V
CD Output Voltage Carrier not present 2.4 V
Carrier present 0.4 V
MUTE Input Voltage Min to mute outputs 2.0 V
Max to force outputs active 0.8 V
ICC Supply Current 85 100 mA

6.6 AC Electrical Characteristics

over Supply Voltage and Operating Temperature ranges, unless otherwise specified(2)(8)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BRMIN Minimum Input Data Rate (SDI, SDI) 143 Mbps
BRMax Maximum Input Data Rate (SDI, SDI) 2970 Mbps
TJRaw Jitter for Various Cable Lengths 270 Mbps, Belden 1694A,
0 to 400 meters(5)		 0.2 UI
270 Mbps, Belden 1694A,
0 to 400 meters(6)		 0.07
1.485 Gbps, Belden 1694A,
0 to 140 meters(5)		 0.25
1.485 Gbps, Belden 1694A,
0-140 meters(6)		 0.08
2.97 Gbps, Belden 1694A,
0 to 120 meters(5)		 0.3
2.97 Gbps, Belden 1694A,
0 to 120 meters(6)		 0.18
tr,tf Output Rise Time, Fall Time (SDO, SDO) 20% to 80%(3) 60 130 ps
TR_F_Delta Mismatch in Rise/Fall Time (SDO, SDO) See  (3) 2 15 ps
tOS Output Overshoot (SDO, SDO) See  (3) 1% 5%
ROUT Output Resistance (SDO, SDO) single-ended 50 Ω
RLIN Input Return Loss (SDI, SDI) 5 MHz
to 1.5 GHz(7)		 15 dB
1.5 GHz
to 3.0 GHz(7)		 10 dB
RIN Input Resistance (SDI, SDI) single-ended 1.3 kΩ
CIN Input Capacitance (SDI, SDI) single-ended 1 pF
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VEE = 0 Volts.
(2) Typical values are stated for VCC = +3.3 V and TA = +25°C.
(3) Specification is ensured by characterization.
(4) This specification is for 1m cable only.
(5) Based on characterization data over the full range of recommended operating conditions of the device. Jitter is measured in accordance with RP 184, RP 192, and the applicable serial data transmission standard: ST 424, ST 292, or ST 259.
(6) Measured with Pseudo Matrix Pathological test signal.
(7) Input return loss is dependent onboard design. The LMH0344 exceeds this specification on the SD344 evaluation board with a return loss network consisting of an 8.2-nH inductor in parallel with a 0.5-pF capacitor in parallel with the 75Ω series resistor on the input.
(8) Due to SMPTE naming convention, all SMPTE Engineering Documents will be numbered as a two-letter prefix and a number. Documents and references with the same root number and year are functionally identical; for example ST 424-2006 and SMPTE 424M-2006 refer to the same document.

6.7 Typical Characteristics

LMH0344 20199004-1.gif
Figure 1. Serial Data Output After Equalizing 120 m of Belden 1694A 2.97-Gbps PRBS10
LMH0344 20199005-1.gif
Figure 2. Serial Data Output After Equalizing 120 m of Belden 1694A 2.97-Gbps Pseudo Matrix Pathological

7 Detailed Description

7.1 Overview

The LMH0344 3-Gbps HD–SD SDI Adaptive Cable Equalizer is designed to equalize data transmitted over cable or any other media with similar dispersive loss characteristics. The equalizer operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, and ST 259.

7.2 Functional Block Diagram

LMH0344 20199002.gif

7.3 Feature Description

7.3.1 Block Description

The Equalizer Filter block is a multistage adaptive filter. If BYPASS is high, the equalizer filter is disabled.

The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If BYPASS is high, this function is disabled.

The signals before and after the DC Restoration / Level Control block are used to generate the Automatic Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter. The loop response in the AEC block is controlled by an external 1-µF capacitor placed across the AEC+ and AEC– pins.

The Carrier Detect / Mute block generates the carrier detect signal and controls the mute function of the output. This block uses the CD and MUTE signals along with Mute Reference (MUTEREF).

The Output Driver produces SDO and SDO.

7.3.2 Mute Reference (MuteREF)

The mute reference sets the threshold for CD and (with CD tied to MUTE) determines the amount of cable to equalize before automatically muting the outputs. This is set by applying a voltage inversely proportional to the length of cable to equalize. The applied voltage must be greater than the MUTEREF floating voltage (typically 1.3 V) to change the CD threshold. As the applied MUTEREF voltage is increased, the amount of cable that can be equalized before carrier detect is deasserted and the outputs are muted is decreased. MUTEREF may be left unconnected or connected to ground for maximum equalization before muting.

7.3.3 Carrier Detect (CD) and Mute

Carrier detect CD indicates if a valid signal is present at the LMH0344 input. If MUTEREF is used, the carrier detect threshold will be altered accordingly. CD provides a high voltage when no signal is present at the LMH0344 input. CD is low when a valid input signal is detected.

MUTE can be used to manually mute or enable SDO and SDO. Applying a high input to MUTE will mute the LMH0344 outputs by forcing the output to a logic zero. Applying a low input will force the outputs to be active.

CD and MUTE may be tied together to automatically mute the output when no input signal is present.

7.3.4 Input Interfacing

The LMH0344 accepts either differential or single-ended input. The input must be AC-coupled. Transformer coupling is not supported.

The LMH0344 correctly handles equalizer pathological signals for standard definition and high definition serial digital video, as described in SMPTE RP 178 and RP 198, respectively.

7.3.5 Output Interfacing

The SDO and SDO outputs are internally loaded with 50 Ω. These outputs produce a 750-mVP-P differential output, or a 375-mVP-P single-ended output.

7.4 Device Functional Modes

The LMH0344 features can be programmed using pin mode only.

 
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