SNLS270L August   2007  – January 2016 LMH0356

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 AC Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Functional Block Description
        1. 8.3.1.1 Serial Data Input and Outputs
        2. 8.3.1.2 Operating Serial Data Rates
        3. 8.3.1.3 Serial Data Clock/Serial Data 2 Output
      2. 8.3.2 Control Inputs and Indicator Outputs
        1. 8.3.2.1 Serial Data Rate Selector
        2. 8.3.2.2 Serial Data Input Selector
        3. 8.3.2.3 Lock Detect
        4. 8.3.2.4 OUTPUT MUTE
        5. 8.3.2.5 Bypass/AUTO BYPASS
        6. 8.3.2.6 SD/HD
        7. 8.3.2.7 SCO_EN
        8. 8.3.2.8 ENABLE
        9. 8.3.2.9 Crystal or External Clock Reference
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Output Interfacing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Figure 11 shows a typical PCB layout for the 48-pin WQFN version of the LMH0356. The following guidelines are recommended for designing the board layout for the LMH0356:

  1. Choose a suitable board stack-up such that it supports 100-Ω differential trace routing on board layer 1. This is typically done with layer 2 ground plane reference for the 100-Ω differential traces.
  2. Place 56-nF loop filter capacitor as close to the loop filter pins as possible.
  3. Use coupled differential traces with 100-Ω ± 5% impedance for signal routing to SDI± and SDO± pins. These are usually 5 to 8-mil trace width reference to a ground plane at layer 2.
  4. DAP of the package must be connected to the ground plane through an array of via. These nine vias are solder-masked to avoid solder flowing into the plated-through holes during the board manufacturing process. DAP is divided into 16 squares (1.09 mm × 1.09 mm) inside 5.1-mm × 5.1-mm landing pad.
  5. Connect supply pins VCC and VEE to the power and ground planes with short via. The via is usually placed tangent to the supply pin landing pad with the shortest trace possible.
  6. Power supply bypass capacitors must be placed close to the supply pin. They are commonly placed at the bottom layer sharing the ground connector of the DAP.

11.2 Layout Example

Figure 11 shows a typical PCB layout for the 48-pin WQFN version of the LMH0356.

LMH0356 lmh0356_layout_guideline_snls270.gif Figure 11. LMH0356 PCB Layout Example