The LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver provides a single chip interface to a BNC. The device can be configured either in the input mode as an equalizer to receive data over coaxial cable or in the output mode as a cable driver to transmit data over coaxial cable. The same I/O pin is used both for the input and the output functions of the device, allowing the system designer the flexibility to use a BNC attached to the device as either an input or an output.
The device operates over a wide range of data rates from 125 Mbps to 2.97 Gbps (DC to 2.97 Gbps when driving cable) and supports ST 424, ST 292, ST 344, and ST 259. The return loss network is integrated within the device so no external components are required to meet the SMPTE return loss specification. The LMH0387 offers designers flexibility in system design and quicker time to market.
In the input mode, the LMH0387 features include a power-saving sleep mode, programmable output common mode voltage and swing, cable length indication, launch amplitude optimization, input signal detection, and an SPI interface. In the output mode, the LMH0387 features include two selectable slew rates for ST 424 / 292 and ST 259 compliance, and output driver power-down control.
The device is available in a 7-mm × 7-mm 48-pin laminate Thin Laminate Grid Array (TLGA) Package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMH0387 | TLGA (48) | 7.00 mm × 7.00 mm |
Changes from G Revision (April 2013) to H Revision
Changes from F Revision (April 2013) to G Revision
PIN | I/O, TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AEC+, AEC- | 20, 21 | I/O, Analog | AEC loop filter external capacitor for equalizer (1 µF connected between AEC+ and AEC-). |
BNC_IO | 8 | I/O, Analog | Serial digital interface input or output for connection to a BNC. Connect this pin to the BNC through an AC coupling capacitor (nominally 4.7 μF). |
CD | 22 | O, LVCMOS | Carrier detect for BNC_IO pin. H = No input signal detected on BNC_IO pin. L = Input signal detected on BNC_IO pin. |
CDTHRESH | 23 | I, Analog | Carrier detect threshold input. Sets the threshold for CD. CDTHRESH may be either unconnected or connected to ground for normal CD operation. |
MISO (SPI) | 29 | O, LVCMOS | SPI Master Input / Slave Output. LMH0387 control data transmit. |
MOSI (SPI) | 39 | I, LVCMOS | SPI Master Output / Slave Input. LMH0387 control data receive. |
RREF | 36 | I, Analog | BNC_IO output driver level control. Connect a resistor (nominally 715 Ω) to VCC to set the output voltage swing for the BNC_IO pin. |
RSVD | 1, 4-7, 9–16, 42, 46-48 | N/A | Do not connect. |
SCK (SPI) | 38 | I, LVCMOS | SPI serial clock input. |
SD/HD | 44 | I, LVCMOS | BNC_IO output slew rate control. SD/HD has an internal pulldown. H = BNC_IO output rise/fall time complies with SMPTE 259M (SD). L = BNC_IO output rise/fall time complies with SMPTE 424M / 292M (3G/HD). |
SDI, SDI | 33, 34 | I, Analog | Serial data differential input for transmitter (cable driver). |
SDO, SDO | 27, 28 | O, LVDS | Serial data differential output from receiver (equalizer). |
SPI_EN | 18 | I, LVCMOS | SPI register access enable (equalizer). This pin should always be high; it must be pulled high while operating in the input mode and may optionally be pulled high while operating in the output mode. This pin has an internal pulldown. |
SS (SPI) | 26 | I, LVCMOS | SPI slave select. This pin has an internal pullup. |
TERMRX | 17 | I, Analog | Termination for unused receiver (equalizer) input. This network should consist of a 1-µF capacitor followed by a 220-Ω resistor to ground. |
TERMTX | 45 | O, Analog | Termination for unused transmitter (cable driver) output. This network should consist of a 4.7-µF capacitor followed by a 75-Ω resistor to ground. |
TX_EN | 40 | I, LVCMOS | Transmitter output driver enable. TX_EN has an internal pullup. H = BNC_IO output driver is enabled. L = BNC_IO output driver is powered off. To configure the LMH0387 as a receiver, the BNC_IO output driver must be disabled by tying TX_EN low. To configure the LMH0387 as a transmitter, the output driver must be enabled by tying TX_EN high and the receiver may be powered down using the sleep mode setting through the SPI. |
VCCTX | 2, 3, 43 | Power | Positive power supply for transmitter (3.3 V). |
VEE | 19, 24, 25, 31, 32, 35, 37, 41 | Power | Negative power supply (ground). |
VCCRX | 30 | Power | Positive power supply for receiver (3.3 V). |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage | 4 | V | ||
Input Voltage (all inputs) | −0.3 | VCC+0.3 | V | |
Junction Temperature | 125 | °C | ||
Storage Temperature | −65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±6000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±2500 | |||
Machine model | ±300 |
MIN | NOM | MAX | UNIT | |
---|---|---|---|---|
Supply Voltage (VCC – VEE) | 3.14 | 3.3 | 3.46 | V |
BNC_IO Input / Output Coupling Capacitance | 4.7 | µF | ||
AEC Capacitor (Connected between AEC+ and AEC-) | 1 | µF | ||
Operating Free Air Temperature (TA) | −40 | 85 | °C |
THERMAL METRIC(1) | LMH0387 | UNIT | |
---|---|---|---|
NPD (TLGA) | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 64.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 20.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 32.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 32 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | Input Voltage High Level | 2 | VCC | V | ||
VIL | Input Voltage Low Level | VEE | 0.8 | V | ||
VOH | Output Voltage High Level | IOH = –2 mA | 2.4 | V | ||
VOL | Output Voltage Low Level | IOL = 2 mA | 0.4 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIN | Input Voltage Swing | 0-m cable length(4) | 720 | 800 | 950 | mVP−P |
VSSP-P | Differential Output Voltage, P-P | 100-Ω load, default register settings, Figure 1(5) | 500 | 700 | 900 | mVP-P |
VOD | Differential Output Voltage | 250 | 350 | 450 | mV | |
ΔVOD | Change in Magnitude of VOD for complementary Output States | 50 | mV | |||
VOS | Offset Voltage | 1.125 | 1.25 | 1.375 | V | |
ΔVOS | Change in Magnitude of VOS for complementary Output States | 50 | mV | |||
IOS | Output Short Circuit Current | 30 | mA | |||
CDTHRESH | CDTHRESH DC Voltage (floating) | 1.3 | V | |||
CDTHRNG | CDTHRESH Range | 0.8 | V | |||
ICC | Supply Current | Equalizing cable > 120 m (Belden 1694A), TX_EN = 0 |
91 | 113 | mA | |
Equalizing cable ≤ 120 m (Belden 1694A), TX_EN = 0(6) |
71 | mA | ||||
Power save mode (equalizer in sleep mode, TX_EN = 0) | 11 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VCMOUT | BNC_IO Output Common Mode Voltage | VCC – VOUT | V | |||
VOUT | BNC_IO Output Voltage Swing | RREF = 715 Ω ±1% | 720 | 800 | 880 | mVP-P |
VCMIN | SDI, SDI Input Common Mode Voltage | 0.9 + VID/2 | VCC – VID/2 | V | ||
VID | SDI, SDI Input Voltage Swing | Differential | 100 | 2200 | mVP-P | |
ICC | Supply Current | SD/HD = 0, equalizer in sleep mode | 57 | 71 | mA | |
SD/HD = 1, equalizer in sleep mode | 50 | mA | ||||
Power save mode (TX_EN = 0, equalizer in sleep mode) | 11 | mA | ||||
Loopback mode (Tx and Rx both enabled), SD/HD = 0 | 117 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DRMIN | Minimum Input Data Rate | 125 | Mbps | |||
DRMAX | Maximum Input Data Rate | 2970 | Mbps | |||
tjit | Equalizer Jitter for Various Cable Lengths (SDO, SDO) | 2.97 Gbps, Belden 1694A, 0-100 meters(7)(8) |
0.3 | UI | ||
2.97 Gbps, Belden 1694A, 100-120 meters(8) |
0.35 | UI | ||||
1.485 Gbps, Belden 1694A, 0-170 meters(7)(8) |
0.25 | UI | ||||
1.485 Gbps, Belden 1694A, 170-200 meters(8) |
0.3 | UI | ||||
270 Mbps, Belden 1694A, 0-350 meters(7)(8) |
0.2 | UI | ||||
270 Mbps, Belden 1694A, 350-400 meters(8) |
0.2 | UI | ||||
tr, tf | Output Rise Time, Fall Time | 20% – 80%, 100 Ω load, Figure 1(3) | 80 | 130 | ps | |
Δtr, Δtf | Mismatch in Rise/Fall Time(3) | . | 2 | 15 | ps | |
tOS | Output Overshoot(3) | 1% | 5% | |||
RLIN | BNC_IO Return Loss | 5 MHz - 1.5 GHz(3)(9) | 15 | dB | ||
1.5 GHz - 3 GHz(3)(9) | 10 | dB |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DRMAX | Maximum Input Data Rate | 2970 | Mbps | |||
tjit | Additive Jitter | 2.97 Gbps(10) | 20 | psP-P | ||
1.485 Gbps(10) | 18 | psP-P | ||||
270 Mbps(10) | 15 | psP-P | ||||
tr, tf | Output Rise Time, Fall Time | SD/HD = 0, 20% – 80% | 65 | 130 | ps | |
SD/HD = 1, 20% – 80% | 400 | 800 | ps | |||
Δtr, Δtf | Mismatch in Rise/Fall Time | SD/HD = 0 | 30 | ps | ||
SD/HD = 1 | 50 | ps | ||||
Duty Cycle Distortion | SD/HD = 0(3) | 30 | ps | |||
SD/HD = 1(3) | 100 | ps | ||||
tOS | Output Overshoot | SD/HD = 0(3) | 10% | |||
SD/HD = 1(3) | 8% | |||||
RLOUT | BNC_IO Output Return Loss | 5 MHz - 1.5 GHz(3)(9) | 15 | dB | ||
1.5 GHz - 3 GHz(3)(9) | 10 | dB |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSCK | SCK Frequency | 20 | MHz | |||
tPH | SCK Pulse Width High | Figure 2, Figure 3 | 40% | SCK period | ||
tPL | SCK Pulse Width Low | 40% | SCK period | |||
tSU | MOSI Setup Time | Figure 2, Figure 3 | 4 | ns | ||
tH | MOSI Hold Time | 4 | ns | |||
tSSSU | SS Setup Time | Figure 2, Figure 3 | 4 | ns | ||
tSSH | SS Hold Time | 4 | ns | |||
tSSOF | SS Off Time | 10 | ns | |||
tODZ | MISO Driven-to-Tristate Time | Figure 3 | 15 | ns | ||
tOZD | MISO Tristate-to-Driven Time | 15 | ns | |||
tOD | MISO Output Delay Time | 15 | ns |
120m 0f B1694A at 2.97 Gbps, PRBS10 H: 100 ps / div, V: 50 mV / div (SDO Output Shown) |
H: 62.5 ps / div, V: 100 mV / div (BNC_IO Output Shown) | ||
The LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver provides a single chip interface to a BNC. The same I/O pin is used both for the input and the output functions of the device, allowing the system designer to use a BNC attached to the device as either an input or an output. The LMH0387 operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, ST 259, and DVB/ASI standards. The LMH0387 includes passive components for the return loss network – simplifying board design and development time.
The LMH0387 can be configured either in the input mode as an equalizer to receive data over coaxial cable or in the output mode as a cable driver to transmit data over coaxial cable. The LMH0387 requires register programming to operate either in Input Mode (Equalizer) or Output Mode (Cable Driver).
SPI register access is required while operating the LMH0387 in the input mode. The equalizer launch amplitude fine tuning must be set to nominal through the SPI for correct equalizer operation. To do this, write 30h (“00110000 binary”) to SPI register 02h. The SPI registers provide access to many other useful LMH0387 features while in the input mode. Refer to the Input Mode (Equalizer) SPI Register Access section for details.
The LMH0387 accepts a single-ended input at the BNC_IO pin. The input must be AC coupled as shown in Figure 9 . The TERMRX input must be properly terminated with a 1-µF capacitor followed by a 220-Ω resistor to ground.
The LMH0387 BNC_IO input can be optimized for different launch amplitudes through the SPI (see Launch Amplitude Optimization (Register 02h) in the Input Mode (Equalizer) SPI Register Access section).
The LMH0387 correctly handles equalizer pathological signals for standard and high definition serial digital video, as described in ST RP 178 and RP 198, respectively.
The LMH0387 equalizer outputs, SDO and SDO, are internally terminated 100-Ω LVDS outputs. These outputs can be DC coupled to most common differential receivers.
The default output common mode voltage (VOS) is 1.25 V. The output common mode voltage may be adjusted through the SPI in 200 mV increments, from 1.05 V to 1.85 V (see Output Driver Adjustments (Register 01h) in the Input Mode (Equalizer) SPI Register Access section). This adjustable output common mode voltage offers flexibility for interfacing to many types of receivers.
The default differential output swing (VSSP-P) is 700 mVP-P. The differential output swing may be adjusted through the SPI in 100 mV increments from 400 mVP-P to 800 mVP-P (see Output Driver Adjustments (Register 01h) in the Input Mode (Equalizer) SPI Register Access section).
The LMH0387 equalizer output should be DC coupled to the input of the receiving device as long as the common mode ranges of both devices are compatible. 100-Ω differential transmission lines should be used to connect between the LMH0387 outputs and the input of the receiving device where possible.
The LMH0387 allows flexibility when interfacing to low voltage crosspoint switches (that is, 1.8 V) and other devices with limited input ranges. The LMH0387 equalizer outputs can be DC coupled to these devices in most cases.
The LMH0387 may be AC coupled to the receiving device when necessary. For example, the LMH0387 equalizer outputs are not strictly compatible with 3.3 V CML and thus should not be connected through 50-Ω resistors to 3.3 V. If the input common mode range of the receiving device is not compatible with the output common mode range of the LMH0387, then AC coupling is required. Following the AC coupling capacitors, the signal may have to be biased at the input of the receiving device.
Carrier detect CD indicates if a valid signal is present at the LMH0387 BNC_IO pin. If CDTHRESH is used, the carrier detect threshold will be altered accordingly. CD provides a high voltage when no signal is present at the LMH0387 BNC_IO pin. CD is low when a valid input signal is detected.
The CDTHRESH pin sets the threshold for the carrier detect. The carrier detect threshold is set by applying a voltage inversely proportional to the length of cable to equalize before loss of carrier is triggered. The applied voltage must be greater than the CDTHRESH floating voltage (typically 1.3 V) to change the CD threshold. As the applied CDTHRESH voltage is increased, the amount of cable that will be equalized before carrier detect is deasserted is decreased. CDTHRESH may be left unconnected or connected to ground for normal CD operation.
Figure 7 shows the minimum CDTHRESH input voltage required to force carrier detect to inactive vs. Belden 1694A cable length. The results shown are valid for Belden 1694A cable lengths of 0 m to 120 m at 2.97 Gbps, 0 m to200 m at 1.485 Gbps, and 0 m to 400 m at 270 Mbps.
The LMH0387 equalizer is set for auto sleep operation by default. The equalizer portion of the LMH0387 powers down when no input signal is detected on the BNC_IO pin. The equalizer powers on again once an input signal is detected. The auto sleep functionality can be changed to force sleep or turned off completely through the SPI registers.
In auto sleep mode, the time to power down the equalizer when the input signal is removed is less than 200 µs and should not have any impact on the system timing requirements. The equalizer will wake up automatically once an input signal is detected, and the delay between signal detection and full functionality of the equalizer is negligible. The overall system will be limited only by the settling time constant of the equalizer adaptation loop.
The LMH0387 cable driver accepts differential input signals which can be DC or AC coupled.
The LMH0387 cable driver uses 75-Ω internally terminated current mode outputs. The output level is 800 mVP-P with an RREF resistor of 715 Ω. The RREF resistor is connected between the RREF pin and VCC, and should be placed as close as possible to the RREF pin.
The output should be AC coupled as shown in the Figure 9. The TERMTX output must be properly terminated with a 4.7-µF capacitor followed by a 75-Ω resistor to ground as shown.
The LMH0387 cable driver output rise and fall times are selectable for either ST 259 or ST 424 / 292 compliance through the SD/HD pin. For slower rise and fall times, or ST 259 compliance, SD/HD is set high. For faster rise and fall times, or ST 424 and ST 292 compliance, SD/HD is set low. SD/HD has an internal pulldown.
The LMH0387 cable driver can be enabled or disabled with the TX_EN pin. When set low, the cable driver is powered off. TX_EN has an internal pullup to enable the cable driver by default. When using the LMH0387 in the input mode (as an equalizer), the cable driver must be disabled by setting the TX_EN pin low.
SPI register access is required while operating the LMH0387 in the input mode. The equalizer launch amplitude fine tuning must be set to nominal through the SPI for correct equalizer operation. To do this, write 30h (“00110000 binary”) to SPI register 02h. The SPI registers provide access to many other useful LMH0387 features while in the input mode.
To configure the LMH0387 in the output mode, the cable driver must be enabled. The equalizer may either be disabled for power savings or enabled to provide a loopback path for the data being transmitted. For the normal output mode (equalizer disabled for power savings) follow these steps:
The LMH0387 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver is used at the input or output port of digital video equipment. It is designed to allow the sharing of a single BNC connector for either input or output. The LMH0387 must be configured in either the output mode as a cable driver, or the input mode as an equalizer.
To configure the LMH0387 in the output mode, the cable driver must be enabled. The equalizer may either be disabled for power savings or enabled to provide a loopback path for the data being transmitted. For the normal output mode (equalizer disabled for power savings) follow these steps:
To configure the LMH0387 for the output mode with the loopback path, the equalizer can be enabled in output mode by writing either “01” (auto sleep – default) or “00” (never sleep) to bits [4:3] of SPI register 00h. In this case, the LMH0387 input/output mode may be configured simply by toggling the TX_EN pin because the equalizer remains active in either mode (TX_EN set low for input mode and high for output mode).
To configure the LMH0387 in the input mode, the equalizer must be enabled and the cable driver must be disabled as described in the following steps:
SPI register access is required for correct input mode (equalizer) operation. The SPI registers provide access to all of the equalizer features along with a cable length indicator, programmable output common mode voltage and swing, and launch amplitude optimization. There are four supported 8-bit registers in the device (see SPI Registers).
Note: The SPI_EN pin must always be pulled high while using the LMH0387 in the input mode (equalizer), and may optionally be pulled high while using the LMH0387 in the output mode (cable driver) as well.
The SPI write is shown in Figure 2. The MOSI payload consists of a “0” (write command), seven address bits, and eight data bits. The SS signal is driven low, and the 16 bits are sent to the LMH0387's MOSI input. Data is latched on the rising edge of SCK. The MISO output is normally tri-stated during this operation. After the SPI write, SS must return high.
The SPI read is shown in Figure 3. The MOSI payload consists of a “1” (read command) and seven address bits. The SS signal is driven low, and the eight bits are sent to the LMH0387's MOSI input. The addressed location is accessed immediately after the rising edge of the 8th clock and the eight data bits are shifted out on MISO starting with the falling edge of the 8th clock. MOSI must be tri-stated immediately after the rising edge of the 8th clock. After the SPI read, SS must return high.
The equalizer output driver swing (amplitude) and offset voltage (common mode voltage) are adjustable through SPI register 01h.
The output swing is adjustable through bits [7:5] of SPI register 01h. The default value for these register bits is “011” for a peak-to-peak differential output voltage of 700 mVP-P. The output swing can be adjusted in 100 mV increments from 400 mVP-P to 800 mVP-P.
The offset voltage is adjustable through bits [4:2] of SPI register 01h. The default value for these register bits is “001” for an output offset of 1.25 V. The output common mode voltage may be adjusted in 200 mV increments, from 1.05 V to 1.85 V. It can also be set to “101” for the maximum offset voltage. At this maximum offset voltage setting, the outputs are referenced to the positive supply and the offset voltage is around 2.1 V.
The LMH0387 can compensate for attenuation of the input signal before the equalizer. This compensation is useful for applications with a passive splitter at the equalizer input or a non-ideal input termination network, and is controlled by SPI register 02h.
NOTE
For correct equalizer operation with the default SMPTE 800 mVP-P launch amplitude and no external attenuation, the equalizer launch amplitude fine tuning must be set to the “nominal” setting through the SPI. To do this, write 30h (“00110000” binary) to SPI register 02h.
Bit 7 of SPI register 02h is used for coarse control of the launch amplitude setting. At the default setting of “0”, the equalizer operates normally and expects a launch amplitude of 800 mVP-P. Bit 7 may be set to “1” to optimize the equalizer for input signals with 6 dB of attenuation (400 mVP-P).
Once the coarse control is set, the equalizer input compensation may be further fine tuned by bits [6:3] of SPI register 02h. These bits may be used to tweak the input gain stage -2% to 60% around the coarse control setting. For typical equalizer operation, bits [6:3] of SPI register 02h should be changed from the default setting of “0000” to the nominal setting of “0110”.
The Cable Length Indicator (CLI) provides an indication of the length of cable attached to the equalizer input. CLI is accessible through bits [7:3] of SPI register 03h. The 5-bit CLI ranges in decimal value from 0 to 25 (“00000” to “11001” binary) and increases as the cable length is increased. Figure 8 shows typical CLI values vs. Belden 1694A cable length. CLI is valid for Belden 1694A cable lengths of 0 m to 120 m at 2.97 Gbps, 0 m to 200 m at 1.485 Gbps, and 0 m to 400 m at 270 Mbps.
SPI Register 00h, General Control, provides access to many basic features of the equalizer, including the carrier detect status and the mute, sleep mode, and extended 3G reach mode controls.
This bit shows the status of the carrier detect for the BNC_IO pin.
The mute control can be used to manually mute or enable SDO and SDO. Setting this bit to “1” will mute the equalizer outputs by forcing them to logic zero. Setting the mute bit to “0” will force the equalizer outputs to be active.
The sleep mode is used to automatically or selectively power down the equalizer for power savings when it is not needed. The auto sleep mode allows the equalizer to power down when no input signal is detected, and is activated by default or by writing “01” to bits [4:3] of SPI register 00h. If the auto sleep mode is active, the equalizer goes into a deep power save mode when no input signal is detected on the BNC_IO pin. The device powers on again once an input signal is detected. The sleep functionality can be turned off completely (equalizer will never sleep) by writing “00” to bits [4:3] of SPI register 00h. Additionally, the equalizer can be forced to power down regardless of whether there is an input signal or not by writing “10” to bits [4:3] of SPI register 00h. The sleep mode has precedence over the mute mode.
The LMH0387 equalizer provides a mode to extend the 3G cable reach in systems that have margin in the jitter budget. This allows for additional cable reach at 2.97 Gbps at the expense of slightly higher output jitter. The extended 3G reach mode provides 10m of additional Belden 1694A cable reach, with an increase of output jitter at this longer cable length of 0.05 to 0.1 UI. (Note: In Extended 3G Reach Mode, the maximum equalizable cable lengths for HD and SD data rates will be limited to less than what can be achieved in normal mode).
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LMH0387 is a single channel SDI cable driver and equalizer that supports different application spaces. The following sections describe the typical use cases and common implementation practices.
The LMH0387 supports SPI interface for configuring the device. Registers must be programmed (see Programming) for proper operation of the device. Attention must be paid to the PCB layout for the high speed signals to facilitate the SMPTE specification compliance. SMPTE specifies requirements for the Serial Digital Interface to transport digital video over coaxial cable. SMPTE specifies the use of AC coupling capacitors for transporting uncompressed serial data with heavy low-frequency content. This specification requires the use of a 4.7-μF AC coupling capacitor to avoid low-frequency DC wander. The 75-Ω trace impedance is required to meet SMPTE specified rise/fall requirements to facilitate highest eye opening for the receiving device.
To meet SMPTE requirements, the optimal placement of the LMH0387 is to be as close to the BNC as possible. Figure 9 shows the application circuit for the LMH0387.
Table 2 lists the key design parameters of the LMH0387.
DESIGN PARAMETER | REQUIREMENTS |
---|---|
Input AC coupling capacitor | Required. A common type of AC coupling capacitor is 4.7-µF ±10% X7R ceramic capacitor (0402 or 0201 size). |
Trace or via under the device | No trace or via under the device. |
Distance from device to BNC | Keep this distance as short as possible to minimize the parasitic. |
BNC_IO, TERMTX, TERMRX trace impedance | Design single-ended trace impedance with 75 Ω ± 5%. |
SDI, SDI and SDO, SDO differential trace impedance | Design differential trace impedance with 100 Ω ± 5%. |
DC power supply coupling capacitors | To minimize power supply noise, use 0.1-µF shunt across 10-µF capacitors as close to the device as possible. |
To begin the design process, determine the followings: