SNLS312M August   2010  – July 2015 LMH0394

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 SPI Interface AC Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Block Description
      2. 7.3.2 Mute Reference (MuteREF)
      3. 7.3.3 Carrier Detect (CD) and Mute
      4. 7.3.4 Input Interfacing
      5. 7.3.5 Output Interfacing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto Sleep
    5. 7.5 Programming
      1. 7.5.1 SPI Register Access
        1. 7.5.1.1  SPI Transaction Overview
        2. 7.5.1.2  SPI Write
        3. 7.5.1.3  SPI Read
        4. 7.5.1.4  SPI Daisy-Chain Operation
        5. 7.5.1.5  SPI Daisy-Chain Write
        6. 7.5.1.6  SPI Daisy-Chain Read
        7. 7.5.1.7  SPI Daisy-Chain Read and Write Example
        8. 7.5.1.8  SPI Daisy-Chain Length Detection
        9. 7.5.1.9  Output Driver Adjustments and De-emphasis Setting
        10. 7.5.1.10 Launch Amplitude Optimization
        11. 7.5.1.11 Cable Length Indicator (CLI)
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Interfacing to 3.3-V SPI
      2. 8.1.2 Crosstalk Immunity
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Dont's
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

For information on layout and soldering of the WQFN package, please refer to the following application note: AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

The ST 424, 292, and 259 standards have stringent requirements for the input return loss of receivers, which essentially specify how closely the input must resemble a 75-Ω network. Any non-idealities in the network between the BNC and the equalizer will degrade the input return loss. Care must be taken to minimize impedance discontinuities between the BNC and the equalizer to ensure that the characteristic impedance of this trace is 75 Ω. Please consider the following PCB recommendations:

  • Use surface mount components, and use the smallest components available. In addition, use the smallest size component pads.
  • Select trace widths that minimize the impedance mismatch between the BNC and the equalizer.
  • Select a board stack-up that supports both 75-Ω single-ended traces and 100-Ω loosely-coupled differential traces.
  • Place return loss components closest to the equalizer input pins.
  • Maintain symmetry on the complementary signals.
  • Route 100-Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
  • Avoid sharp bends in the signal path; use 45° or radial bends.
  • Place bypass capacitors close to each power pin, and use the shortest path to connect equalizer power and ground pins to the respective power or ground planes.

10.2 Layout Example

Figure 22 and Figure 21 demonstrate the LMH0394EVM PCB layout. Ground and supply relief under the return loss passive components and pads reduces parasitic - improving return loss performance. The solder mask for the DAP is divided into four quadrants. Five via are placed such that they are in the boundary of the 4 quadrants. This is done to ensure that the via are not covered by solder mask for improving solder quality. This practice improves both thermal performance and soldering during board assembly.

LMH0394 Layout_Example_1-1.gifFigure 21. LMH0394EVM Top Etch Layout
LMH0394 Layout_Example_1-2.gifFigure 22. LMH0394EVM Top Solder Paste Mask