SNLS558C
April 2017 – May 2020
LMH0397
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Simplified Block Diagram
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Recommended SMBus Interface Timing Specifications
7.7
Serial Parallel Interface (SPI) Timing Specifications
7.8
Typical Characteristics
8
Detailed Description
8.1
Overview
8.1.1
Equalizer Mode (EQ Mode)
8.1.2
Cable Driver Mode (CD Mode)
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
4-Level Input Pins and Thresholds
8.3.2
Equalizer (EQ) and Cable Driver (CD) Mode Control
8.3.2.1
EQ/CD_SEL Control
8.3.2.2
OUT0_SEL and SDI_OUT_SEL Control
8.3.3
Input Carrier Detect
8.3.4
–6-dB Splitter Mode Launch Amplitude for SDI_IO+ (EQ Mode Only)
8.3.5
Continuous Time Linear Equalizer (CTLE)
8.3.5.1
Line-Side Adaptive Cable Equalizer (SDI_IO+ in EQ Mode)
8.3.5.2
Host-Side Adaptive PCB Trace Equalizer (IN0± in CD Mode)
8.3.6
Clock and Data (CDR) Recovery
8.3.7
Internal Eye Opening Monitor (EOM)
8.3.8
Output Function Control
8.3.9
Output Driver Control
8.3.9.1
Line-Side Output Cable Driver (SDI_IO+ in CD Mode, SDI_OUT+ in EQ or CD Mode)
8.3.9.1.1
Output Amplitude (VOD)
8.3.9.1.2
Output Pre-Emphasis
8.3.9.1.3
Output Slew Rate
8.3.9.1.4
Output Polarity Inversion
8.3.9.2
Host-Side 100-Ω Output Driver (OUT0± in EQ or CD Mode)
8.3.10
Status Indicators and Interrupts
8.3.10.1
LOCK_N (Lock Indicator)
8.3.10.2
CD_N (Carrier Detect)
8.3.10.3
INT_N (Interrupt)
8.3.11
Additional Programmability
8.3.11.1
Cable EQ Index (CEI)
8.3.11.2
Digital MUTEREF
8.4
Device Functional Modes
8.4.1
System Management Bus (SMBus) Mode
8.4.1.1
SMBus Read and Write Transaction
8.4.1.1.1
SMBus Write Operation Format
8.4.1.1.2
SMBus Read Operation Format
8.4.2
Serial Peripheral Interface (SPI) Mode
8.4.2.1
SPI Read and Write Transactions
8.4.2.2
SPI Write Transaction Format
8.4.2.3
SPI Read Transaction Format
8.4.2.4
SPI Daisy Chain
8.5
Register Maps
9
Application and Implementation
9.1
Application Information
9.1.1
SMPTE Requirements and Specifications
9.1.2
Low-Power Optimization in CD Mode
9.2
Typical Applications
9.2.1
Bidirectional I/O
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Cable Equalizer With Loop-Through
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Board Stack-Up and Ground References
11.1.2
High-Speed PCB Trace Routing and Coupling
11.1.2.1
SDI_IO± and SDI_OUT±
11.1.2.2
IN0± and OUT0±
11.1.3
Anti-Pads
11.1.4
BNC Connector Layout and Routing
11.1.5
Power Supply and Ground Connections
11.1.6
Footprint Recommendations
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Developmental Support
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Support Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Export Control Notice
12.8
Glossary
13
Mechanical, Packaging, and Orderable Information
13.1
Package Option Addendum
13.1.1
Packaging Information
13.1.2
Tape and Reel Information
Package Options
Mechanical Data (Package|Pins)
RTV|32
MPQF166B
Thermal pad, mechanical data (Package|Pins)
RTV|32
QFND101J
Orderable Information
snls558c_oa
snls558c_pm
2
Applications
SMPTE compatible serial digital interface
UHDTV/4K/8K/HDTV/SDTV video
IP media gateway
Digital video processing and editing