SNLS569C March   2017  – May 2020 LMH1208

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Pins and Thresholds
      2. 7.3.2 OUT0_SEL and SDI_OUT2_SEL Control
      3. 7.3.3 Input Signal Detect
      4. 7.3.4 Continuous Time Linear Equalizer (CTLE)
      5. 7.3.5 Output Driver Control
        1. 7.3.5.1 Line-Side Output Cable Driver (SDI_OUT1+, SDI_OUT2+)
          1. 7.3.5.1.1 Output Amplitude (VOD)
          2. 7.3.5.1.2 Output Pre-Emphasis
          3. 7.3.5.1.3 Output Slew Rate
          4. 7.3.5.1.4 Output Polarity Inversion
        2. 7.3.5.2 Host-Side 100-Ω Output Driver (OUT0±)
      6. 7.3.6 Status Indicators and Interrupts
        1. 7.3.6.1 SD_N (Signal Detect)
        2. 7.3.6.2 INT_N (Interrupt)
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transaction
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
        2. 7.4.2.2 SPI Write Transaction Format
        3. 7.4.2.3 SPI Read Transaction Format
        4. 7.4.2.4 SPI Daisy Chain
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SMPTE Requirements and Specifications
      2. 8.1.2 LMH1208 and LMH1228 Compatibility
    2. 8.2 Typical Applications
      1. 8.2.1 Dual Cable Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Distribution Amplifier
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Stack-Up and Ground References
      2. 10.1.2 High-Speed PCB Trace Routing and Coupling
      3. 10.1.3 Anti-Pads
      4. 10.1.4 BNC Connector Layout and Routing
      5. 10.1.5 Power Supply and Ground Connections
      6. 10.1.6 Footprint Recommendations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Export Control Notice
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.3 Application Curves

The LMH1208 performance on SDI_OUT1+ and SDI_OUT2+ was measured with the test setups shown in Figure 21 and Figure 22.

LMH1208 app_test_setup_diagram_SDIOUT1.gifFigure 21. Test Setup for LMH1208 to SDI_OUT1+
LMH1208 app_test_setup_diagram_SDIOUT2.gifFigure 22. Test Setup for LMH1208 to SDI_OUT2+

The eye diagrams in this subsection show how the LMH1208 improves overall signal integrity in the data path for 100-Ω differential FR4 PCB trace at IN0±.

LMH1208 CD_IO_1inFR4_EQOnly_HOSTEQ0H_11.88_PRBS10_200mV_14ps.png
Measured at SDI_OUT1+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = H
Figure 23. 11.88 Gbps, TL = 1" FR4
LMH1208 CD_IO_1inFR4_EQOnly_HOSTEQ0H_5.94_PRBS10_200mV_28ps.png
Measured at SDI_OUT1+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = H
Figure 25. 5.94 Gbps, TL = 1" FR4
LMH1208 CD_IO_2.97G_PRBS10_200mV_56ps.png
Measured at SDI_OUT1+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = F
Figure 27. 2.97 Gbps, TL = 1" FR4
LMH1208 CD_IO_1.485G_PRBS10_200mV_112ps.png
Measured at SDI_OUT1+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = F
Figure 29. 1.485 Gbps, TL = 1" FR4
LMH1208 CD_IO_270M_PRBS10_200mV_617ps.png
Measured at SDI_OUT1+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = L
Figure 31. 270 Mbps, TL = 1" FR4
LMH1208 LMH12x8_CD_SDIOUT_1inFR4_EQOnly_HOSTEQ0H_11.88_PRBS10_200mV_14ps.png
Measured at SDI_OUT2+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = H
Figure 24. 11.88 Gbps, TL = 1" FR4
LMH1208 LMH12x8_CD_SDIOUT_1inFR4_EQOnly_HOSTEQ0H_5.94_PRBS10_200mV_28ps.png
Measured at SDI_OUT2+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = H
Figure 26. 5.94 Gbps, TL = 1" FR4
LMH1208 CD_SDIOUT_2.97G_PRBS10_200mV_56ps.png
Measured at SDI_OUT2+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = F
Figure 28. 2.97 Gbps, TL = 1" FR4
LMH1208 CD_SDIOUT_1.485G_PRBS10_200mV_112ps.png
Measured at SDI_OUT2+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = F
Figure 30. 1.485 Gbps, TL = 1" FR4
LMH1208 CD_SDIOUT_270M_PRBS10_200mV_617ps.png
Measured at SDI_OUT2+
HOST_EQ0 = H, SDI_OUT2_SEL = L, SLEW_CTRL = L
Figure 32. 270 Mbps, TL = 1" FR4