SNLS569C March   2017  – May 2020 LMH1208

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Pins and Thresholds
      2. 7.3.2 OUT0_SEL and SDI_OUT2_SEL Control
      3. 7.3.3 Input Signal Detect
      4. 7.3.4 Continuous Time Linear Equalizer (CTLE)
      5. 7.3.5 Output Driver Control
        1. 7.3.5.1 Line-Side Output Cable Driver (SDI_OUT1+, SDI_OUT2+)
          1. 7.3.5.1.1 Output Amplitude (VOD)
          2. 7.3.5.1.2 Output Pre-Emphasis
          3. 7.3.5.1.3 Output Slew Rate
          4. 7.3.5.1.4 Output Polarity Inversion
        2. 7.3.5.2 Host-Side 100-Ω Output Driver (OUT0±)
      6. 7.3.6 Status Indicators and Interrupts
        1. 7.3.6.1 SD_N (Signal Detect)
        2. 7.3.6.2 INT_N (Interrupt)
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transaction
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
        2. 7.4.2.2 SPI Write Transaction Format
        3. 7.4.2.3 SPI Read Transaction Format
        4. 7.4.2.4 SPI Daisy Chain
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SMPTE Requirements and Specifications
      2. 8.1.2 LMH1208 and LMH1228 Compatibility
    2. 8.2 Typical Applications
      1. 8.2.1 Dual Cable Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Distribution Amplifier
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Stack-Up and Ground References
      2. 10.1.2 High-Speed PCB Trace Routing and Coupling
      3. 10.1.3 Anti-Pads
      4. 10.1.4 BNC Connector Layout and Routing
      5. 10.1.5 Power Supply and Ground Connections
      6. 10.1.6 Footprint Recommendations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Export Control Notice
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Recommended SMBus Interface Timing Specifications

over recommended operating supply and temperature ranges unless otherwise specified(1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
FSCL SMBUS SCL frequency 10 400 kHz
TBUF Bus free time between stop and start condition See Figure 1. 1.3 µs
THD:STA Hold time after (repeated) start condition After this period, the first clock is generated. 0.6 µs
TSU:STA Repeated start condition setup time See Figure 1. 0.6 µs
TSU:STO Stop condition setup time See Figure 1. 0.6 µs
THD:DAT Data hold time See Figure 1. 0 ns
TSU:DAT Data setup time See Figure 1. 100 ns
TLOW Clock low period See Figure 1. 1.3 µs
THIGH Clock high period See Figure 1. 0.6 µs
TR Clock and data rise time See Figure 1. 300 ns
TF Clock and data fall time See Figure 1. 300 ns
TPOR SMBus ready time after POR Time from minimum VDDIO to SMBus valid write or read access 50 ms
(1) These parameters support SMBus 2.0 specifications.