The LMH1219 is a low-power, dual-input and dual-output, adaptive equalizer with integrated reclocker. It supports SMPTE video rates up to 11.88 Gbps and 10 GbE video over IP, enabling UHD video for 4K/8K applications. An extended reach adaptive cable equalizer at IN0 is designed to equalize data transmitted over 75 Ω coaxial cable and operates over a wide range of data rates from 125 Mbps to 11.88 Gbps. An adaptive board trace equalizer at IN1 is SFF-8431 compatible and supports both SMPTE and 10 GbE data rates.
The integrated reclocker attenuates high frequency jitter and provides the best signal integrity. High input jitter tolerance of the reclocker improves timing margin. The reclocker has a built-in loop filter, and operates without the need of a precision input reference clock. A non-disruptive eye monitor allows real time measurement of the serial data to simplify system debug and accelerate board bring-up.
The integrated 2:1 Mux and 1:2 Fanout provide flexibility for multiple video signals. The output drivers offer programmable de-emphasis to compensate board trace losses at its outputs. The integrated return loss network meets stringent SMPTE specifications across all data rates. The typical power consumption of LMH1219 is 250 mW. In the absence of input signal, power is further reduced to 16 mW.
The LMH1219 is pin compatible to LMH1226 (12G UHD reclocker) and LMH0324 (3G adaptive cable equalizer).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMH1219 | QFN (24) | 4.00 mm × 4.00 mm |
Changes from C Revision (October 2017) to D Revision
Changes from B Revision (February 2017) to C Revision
Changes from A Revision (May 2016) to B Revision
Changes from * Revision (April 2016) to A Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
High Speed Differential I/O'S | |||
IN0+ | 1 | I, Analog | Single-ended complementary inputs, 75-Ω internal termination from IN0+ or IN0- to internal common mode voltage and return loss compensation network. Requires external 4.7-µF AC coupling capacitors. IN0+ is the 75-Ω input port for the adaptive cable equalizer in SMPTE video applications. |
IN0- | 2 | I, Analog | |
IN1+ | 4 | I, Analog | Differential complementary inputs with internal 100-Ω termination. Requires external 4.7-µF AC coupling capacitors for SMPTE and 10 GbE. |
IN1- | 5 | I, Analog | |
OUT0+ | 18 | O, Analog | Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user control. |
OUT0- | 17 | O, Analog | |
OUT1+ | 15 | O, Analog | Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user control. |
OUT1- | 14 | O, Analog | |
Control Pins | |||
LOCK_N | 12 | O, LVCMOS, OD | LOCK_N is the reclocker lock indicator for the selected input. LOCK_N is pulled LOW when the reclocker has acquired locking condition. LOCK_N is an open drain output, 3.3 V tolerant, and requires an external 2-kΩ to 5-kΩ pull-up resistor to logic supply. LOCK_N pin can be re-configured to indicate CD_N (Carrier Detect) or INT_N (Interrupt) for IN0 or IN1 through register programming. |
IN_OUT_SEL | 8 | I, 4-LEVEL | IN_OUT_SEL selects the signal flow at input ports to output ports. See Table 2 for details. This pin setting can be overridden by register control. |
OUT_CTRL | 19 | I, 4-LEVEL | OUT_CTRL selects the signal flow from the selected IN port to OUT0± and OUT1±. It selects reclocked data, reclocked data and clock, bypassed reclocker data (equalized data to output driver), or bypassed equalizer and reclocker data. See Table 4 for details. This pin setting can be overridden by register control. |
VOD_DE | 11 | I, 4-LEVEL | VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0± and OUT1±. See Table 5 for details. This pin setting can be overridden by register control. |
MODE_SEL | 6 | I, 4-LEVEL | MODE_SEL enables SPI or SMBus serial control interface. See Table 6 for details. |
Serial Control Interface (SPI Mode), MODE_SEL = F (Float) | |||
SS_N | 7 | I, LVCMOS | SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the LMH1219 slave device. SS_N is a LVCMOS input referenced to VDDIO. |
MISO | 20 | O, LVCMOS | MISO is the SPI control serial data output from the LMH1219 slave device. MISO is a LVCMOS output referenced to VDDIO. |
MOSI | 10 | I, LVCMOS | MOSI is used as the SPI control serial data input to the LMH1219 slave device. MOSI is LVCMOS input referenced to VDDIO. |
SCK | 21 | I, LVCMOS | SCK is the SPI serial input clock to the LMH1219 slave device. SCK is LVCMOS referenced to VDDIO. |
Serial Control Interface (SMBus MODE) , MODE_SEL = L (1 kΩ to VSS) | |||
ADDR0 | 7 | Strap, 4-LEVEL | ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus addresses. ADDR[1:0] are 4-level straps and are read into the device at power up. |
ADDR1 | 20 | Strap, 4-LEVEL | |
SDA | 10 | IO, LVCMOS, OD | SDA is the SMBus bi-directional open drain SDA data line to or from the LMH1219 slave device. SDA is an open drain IO and tolerant to 3.3 V. SDA requires an external 2-kΩ to 5-kΩ pull-up resistor to the SMBus termination voltage. |
SCL | 21 | I, LVCMOS, OD | SCL is the SMBus input clock to the LMH1219 slave device. It is driven by a LVCMOS open drain driver from the SMBus master. SCL is tolerant to 3.3 V and requires an external 2-kΩ to 5-kΩ pull up resistor to the SMBus termination voltage. |
Power | |||
VSS | 3, 9, 16 | I, Ground | Ground reference. |
VIN | 24 | I, Power | VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ± 5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO regulator. For lower power operation, both VIN and VDD_LDO should be connected to a 1.8 V supply. |
VDDIO | 22 | I, Power | VDDIO powers the LVCMOS IO and 4-level input logic and connects to 2.5 V ± 5%. |
VDD_LDO | 23 | IO, Power | VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to a 2.5 V supply. VDD_LDO output requires external 1-µF and 0.1-µF bypass capacitors to VSS. The internal LDO is designed to power internal circuitry only. VDD_LDO is an input when VIN is powered from 1.8 V for lower power operation. When VIN is connected to a 1.8 V supply, both VIN and VDD_LDO should be connected to a 1.8 V supply. |
VDD_CDR | 13 | I, Power | VDD_CDR powers the reclocker circuitry and connects to 2.5 V ± 5% supply. |
EP | I, Ground | EP is the exposed pad at the bottom of the QFN package. The exposed pad must be connected to the ground plane through a via array. See Figure 41 for details. |