SNLS534D April   2016  – June 2018 LMH1226

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Pins
      2. 7.3.2 Input Carrier Detect
      3. 7.3.3 Continuous Time Linear Equalizer (CTLE)
        1. 7.3.3.1 Adaptive PCB Trace Equalizer (IN1±)
      4. 7.3.4 Input-Output Mux Selection
      5. 7.3.5 Clock and Data Recovery (CDR) Reclocker
      6. 7.3.6 Internal Eye Opening Monitor (EOM)
      7. 7.3.7 Output Function Control
      8. 7.3.8 Output Driver Amplitude and De-Emphasis Control
      9. 7.3.9 Status Indicators and Interrupts
        1. 7.3.9.1 LOCK_N (Lock Indicator)
        2. 7.3.9.2 CD_N (Carrier Detect)
        3. 7.3.9.3 INT_N (Interrupt)
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transactions
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
          1. 7.4.2.1.1 SPI Write Transaction Format
          2. 7.4.2.1.2 SPI Read Transaction Format
        2. 7.4.2.2 SPI Daisy Chain
    5. 7.5 LMH1226 Register Map
      1. 7.5.1 Share Register Page
      2. 7.5.2 CTLE/CDR Register Page
      3. 7.5.3 Drivers Register Page
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for SMPTE and 10 GbE Applications
      2. 8.1.2 LMH1219 and LMH1226 Compatibility
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Recommended VOD and DEM Register Settings
      4. 8.2.4 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2 CTLE/CDR Register Page

Address Register Name Bit Field Default Type Description
0x00 Reset CTLE/CDR Registers 7:3 Reserved 0x00 RW Reserved
2 rst_CTLE/CDR_regs RW Reset registers (self-clearing)
0 = Normal Operation
1 = Reset CTLE/CDR Registers. Register re-initialization procedure required after resetting the CTLE/CDR Registers.
1:0 Reserved RW Reserved
0x01 LOS Status 7:2 Reserved 0x03 RW Reserved
1 LOS1 R 0 = Signal Present on IN1
1 = Loss of Signal on IN1
0 Reserved R Reserved
0x02 CDR_Status 7:0 CDR_Status 0x41 R CDR status indicator. See "Lock Data Rate Indication" subsection in the LMH1219 Programming Guide for more information.
0x03 IN1 Manual EQ Boost 7:6 eq_BST0 0x80 RW Used for setting manual EQ value for IN1 when Reg 0x2D[3] = 1. EQ boost value can be read back on CTLE/CDR Page Reg 0x52.
[7:6]: 2-bit control for Stage 0 of the CTLE.
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 eq_BST1 RW
3:2 eq_BST2 RW
1:0 eq_BST3 RW
0x04 Reserved 7:0 Reserved 0x00 RW Reserved
0x05 Reserved 7:0 Reserved 0x00 RW Reserved
0x06 Reserved 7:0 Reserved 0x00 RW Reserved
0x07 Reserved 7:0 Reserved 0x00 RW Reserved
0x08 Reserved 7:0 Reserved 0x00 RW Reserved
0x09 Output Mux Override Control 7:6 Reserved 0x00 RW Reserved
5 reg_out_control_ov RW Output Mux Override Control
0 = Reg 0x1C[3:2] determines the output selection for both OUT0 and OUT1
1 = Enable individual output mux control based on values from Reg 0x1C[7:5] and Reg 0x1E[7:5]
4:3 Reserved RW Reserved
2:0 Reserved RW Reserved
0x0A CDR Reset Control 7:4 Reserved 0x50 RW Reserved
3 reg_cdr_reset_ov RW 0 = Disables CDR Reset (Normal Operating Mode)
1 = Enables Reg 0x0A[2] to control CDR Reset
2 reg_cdr_reset RW 0 = No CDR Reset if Reg 0x0A[3] = 1
1 = CDR Reset if Reg 0x0A[3] = 1
1:0 Reserved RW Reserved
0x0B Reserved 7:0 Reserved 0x1F RW Reserved
0x0C CDR Output Status Control 7:4 reg_sh_status_control 0x08 RW Value determines what CDR status outputs are displayed in CTLE/CDR Page Reg 0x02. See "Lock Data Rate Indication" subsection in the LMH1219 Programming Guide for more information.
3:0 Reserved RW Reserved
0x0D Reserved 7:0 Reserved 0x00 RW Reserved
0x0E Reserved 7:0 Reserved 0x93 RW Reserved
0x0F Reserved 7:0 Reserved 0x69 RW Reserved
0x10 Reserved 7:0 Reserved 0x27 RW Reserved
0x11 EOM Voltage Range Control 7:6 eom_sel_vrange 0xE0 RW Sets the expected incoming eye diagram vertical eye opening interval if Reg 0x2C[6] = 0
00 = 3.125 mV (3.125 mV x 64 = 200 mV; ±100 mV range)
01 = 6.25 mV (6.25 mV x 64 = 400 mV; ±200 mV range)
10 = 9.375 mV (9.375 mV x 64 = 600 mV; ±300 mV range)
11 = 12.5 mV (12.5 mV x 64 = 800 mV; ±400 mV range)
5 eom_PD RW 0 = EOM is always powered up
1 = Power down EOM when not in use
4:0 Reserved RW Reserved
0x12 Reserved 7:0 Reserved 0xA0 RW Reserved
0x13 IN1 Carrier Detect and CTLE Control 7:4 Reserved 0x90 RW Reserved
3 eq_PD_EQ RW IN1 CTLE Power-Down Control
0 = Powers up EQ of IN1
1 = Powers down EQ of IN1
Note: The un-selected channel is always powered-down.
2 Reserved RW Reserved
1 eq_en_bypass RW 0 = Enable Gain Stages 2 and 3 of IN1 CTLE
1 = Bypass Gain Stages 2 and 3 of IN1 CTLE
0 Reserved RW Reserved
0x14 Reserved 7:0 Reserved 0x00 RW Reserved
0x15 IN1 Carrier Detect Threshold Setting 7 Reserved 0x00 RW Reserved
6 cd_1_PD RW IN1 Carrier Detect Power Down Control
0 = Power Up IN1 Carrier Detect
1 = Power Down IN1 Carrier Detect
5:4 cd_1_refa_sel RW Controls IN1 Carrier Detect Assert and De-Assert Thresholds
0000 = Default levels (nominal)
0101 = Nominal - 2 mV
1010 = Nominal + 5 mV
1111 = Nominal + 3 mV
3:2 cd_1_refd_sel RW
1:0 Reserved RW Reserved
0x16 Reserved 7:0 Reserved 0x25 RW Reserved
0x17 Reserved 7:0 Reserved 0x25 RW Reserved
0x18 Reserved 7:0 Reserved 0x40 RW Reserved
0x19 Reserved 7:0 Reserved 0x00 RW Reserved
0x1A Reserved 7:0 Reserved 0xA0 RW Reserved
0x1B Reserved 7:0 Reserved 0x03 RW Reserved
0x1C OUT Mux Select_0 7:5 out_sel0_data_mux 0x58 RW In normal operating mode, Reg 0x1C[7:5] returns the mux select value applied at OUT0.
When Reg 0x09[5] = 1, OUT0 mux selection is controlled by Reg 0x1C[7:5] as follows:
000 = Mute
001 = 10 MHz Clock
010 = Raw Data (EQ Only)
100 = Retimed Data
Other Settings are invalid.
4 VCO_Div40 RW When Reg 0x09[5] = 1 and Reg 0x1E[7:5] = 101'b, OUT1 clock selection can be controlled by Reg 0x1C[4] as follows:
0 = OUT1 outputs 10 MHz clock
1 = OUT1 outputs VCO divide-by-40
3:2 drv_out_ctrl RW Controls output mux selection for both OUT0 and OUT1 if Reg 0x3F[3] = 1 to override the OUT_CTRL pin
00 = Mute both OUT0 and OUT1
01 = When CDR is locked, output reclocked data on OUT0 and output clock on OUT1. If locked data rate is ≤ 3G, OUT1 = VCO. If locked data rate is > 3G, OUT1 = VCO/40. When unlocked, output raw data on OUT0 and mute OUT1.
10 = When locked, output retimed data on both OUT0 and OUT1. When unlocked, output raw data on both OUT0 and OUT1. This is the default setting.
11 = Output raw data on both OUT0 and OUT1.
1:0 Reserved RW Reserved
0x1D Reserved 7:0 Reserved 0x00 RW Reserved
0x1E OUT Mux Select_1 7:5 out_sel1_data_mux 0x09 RW In normal operating mode, Reg 0x1E[7:5] returns the mux select value applied at OUT1.
When Reg 0x09[5] = 1, OUT1 mux selection is controlled by Reg 0x1E[7:5] as follows:
000 = Raw Data (EQ Only)
001 = Retimed Data
010 = Full Rate VCO clock
101 = 10 MHz Clock if Reg 0x1C[4] = 0 and VCO/40 clock if Reg 0x1C[4] = 1
111 = Mute
Other Settings are invalid
4:0 Reserved RW Reserved
0x1F OUT1 Polarity 7 sel_inv_out1 0x10 RW 0 = OUT1 normal polarity
1 = Inverts OUT1 driver polarity
Note: No polarity inversion for OUT0
6:0 Reserved RW Reserved
0x20 Reserved 7:0 Reserved 0x00 RW Reserved
0x21 Reserved 7:0 Reserved 0x00 RW Reserved
0x22 Reserved 7:0 Reserved 0x00 RW Reserved
0x23 HEO_VEO_OV 7 eom_get_heo_
veo_ov		 0x40 RW 0 = Disable HEO/VEO Acquisition override.
1 = Enable HEO/VEO Acquisition override. Value determined by Reg 0x24[1].
6:0 Reserved Reserved
0x24 EOM Control 7 fast_eom 0x40 RW 0 = Disable Fast EOM mode
1 = Enable Fast EOM mode
6 Reserved R Reserved
5 get_heo_veo_error_
no_hits		 R Zero Crossing Error Detector Status
0 = Zero crossing errors in the eye diagram observed
1 = No zero crossing errors in the eye diagram observed
4 get_heo_veo_error_
no_opening		 R Vertical Eye Closure Detector Status
0 = Open eye diagram detected
1 = Eye diagram completely closed
3:2 Reserved R Reserved
1 eom_get_heo_veo RW 1 = Acquire HEO and VEO (self-clearing) if Reg 0x23[7] = 1
0 eom_start RW 1 = Start EOM counter (self-clearing)
0x25 EOM_MSB 7:0 eom_count_msb 0x00 R MSBs of EOM counter
0x26 EOM_LSB 7:0 eom_count_lsb 0x00 R LSBs of EOM counter
0x27 HEO 7:0 heo 0x00 R HEO value. This is measured in 0-63 phase settings. To get HEO in UI, read HEO, convert hex to dec, then divide by 64.
0x28 VEO 7:0 veo 0x00 R VEO value. This is measured in 0-63 vertical steps. To get VEO in mV, convert hex to dec, then multiply by the EOM Voltage Range defined in Reg 0x29[6:5].
0x29 Auto EOM Voltage Range 7 Reserved 0x00 RW Reserved
6:5 eom_vrange_setting R Readback of automatic EOM Voltage Range granularity.
00 = 3.125 mV
01 = 6.25 mV
10 = 9.375 mV
11 = 12.5 mV
4:0 Reserved RW Reserved
0x2A EOM_timer_thr 7:0 eom_timer_thr 0x30 RW EOM timer for how long to check each phase/voltage setting.
0x2B Reserved 7:0 Reserved 0x00 RW Reserved
0x2C VEO Scale 7 Reserved 0x72 RW Reserved
6 veo_scale RW 0 = VEO scaling based on manual Voltage Range settings (see Reg 0x11[7:6])
1 = Enable Auto VEO scaling
5:0 Reserved RW Reserved
0x2D CTLE Boost Override 7:4 Reserved 0x00 RW Reserved
3 reg_eq_bst_ov RW IN1 EQ Boost Override Control
0 = Disable IN1 EQ boost override
1 = Override the internal IN1 EQ boost settings with values in Reg 0x03[7:0]
2:0 Reserved RW Reserved
0x2E Reserved 7:0 Reserved 0x24 RW Reserved
0x2F Rate Overrides 7:6 refn_rate 0x06 RW Reference Rate Selection for CDR Lock if Reg 0x3F[2] = 1
00 = Select SMPTE rates
01 = Select 10G Ethernet rate
Other settings are Invalid
5:0 Reserved R Reserved
0x30 Reserved 7:0 Reserved 0x00 RW Reserved
0x31 IN1 Adaptation Mode and Input Mux Select 7 Reserved 0x00 RW Reserved
6:5 adapt_mode RW Adapt Mode Override Value if Reg 0x3F[5] = 1
00 = Manual CTLE for IN1. Set CTLE/CDR Page Reg 0x2D[3] = 1 to enable IN1 EQ boost settings with values in Reg 0x03[7:0].
01 = Automatic CTLE Adaptation for IN1.
4:2 Reserved RW Reserved
1:0 input_mux_ch_sel RW Input Mux Selection if Reg 0x3F[4] = 1 to override IN_OUT_SEL pin
10 = IN1 to OUT1 only
11 = IN1 to OUT0 and OUT1
Other settings are Invalid
0x32 HEO/VEO Interrupt Threshold 7:4 heo_int_thresh 0x11 RW Compares HEO value, Reg 0x27[7:0] vs. threshold from Reg 0x32[7:4] x 4.
3:0 veo_int_thresh RW Compares VEO value. Reg 0x28[7:0] vs. threshold from Reg 0x32[3:0] x 4.
0x33 Reserved 7:0 Reserved 0x88 RW Reserved
0x34 Reserved 7:0 Reserved 0x3F RW Reserved
0x35 Reserved 7:0 Reserved 0x1F RW Reserved
0x36 Reserved 7:0 Reserved 0x11 RW Reserved
0x37 Reserved 7:0 Reserved 0x00 R Reserved
0x38 Reserved 7:0 Reserved 0x00 R Reserved
0x39 Reserved 7:0 Reserved 0x00 R Reserved
0x3A Low Data Rate IN1 EQ Boost 7:6 fixed_eq_BST0 0x00 RW Fixed IN1 CTLE setting for 270M and 1.5G SMPTE rates. If Reg 0x3F[0] = 0, Reg 0x3A fixed IN1 CTLE setting is also used for 3G rate.
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 fixed_eq_BST1 RW
3:2 fixed_eq_BST2 RW
1:0 fixed_eq_BST3 RW
0x3B Reserved 7:0 Reserved 0x96 R Reserved
0x3C Reserved 7:0 Reserved 0x90 R Reserved
0x3D Reserved 7:0 Reserved 0x00 RW Reserved
0x3E HEO_VEO Lock Monitor Enable 7 heo_veo_lockmon_en 0x80 RW Enable HEO/VEO lock monitoring. Once the lock and adaptation processes are complete, HEO/VEO monitoring is performed once per the interval determined by Reg 0x69[3:0].
6:0 Reserved RW Reserved
0x3F Pin Override Register Control 7:6 Reserved 0x01 RW Reserved
5 mr_adapt_mode_ov RW 0 = Normal Behavior (Automatic Adaptation when IN1 is selected)
1 = Override Automatic Adaptation for IN1. Adaptation behavior is controlled by Reg 0x31[6:5].
4 mr_in_out_sel_ov RW 0 = Input channel selection determined by IN_OUT_SEL pin
1 = Override input channel selection pin settings. Input selection is controlled by Reg 0x31[1:0].
3 mr_out_ctrl_ov RW 0 = Output mux settings determined by OUT_CTRL pin
1 = Override output mux pin settings. Output mux is controlled by Reg 0x1C[3:2].
2 mr_refn_rate_ov RW 0 = SMPTE or 10 GbE reference rates determined by IN_OUT_SEL pin
1 = Override reference rate pin settings. Reference rates for CDR lock are controlled by Reg 0x2F[7:6].
1 mr_eqbst_pin_ov RW 0 = IN1 EQ boost Bypass is controlled by OUT_CTRL pin behavior
1 = Override IN1 EQ boost pin control. IN1 EQ boost bypass characteristics are controlled by settings in Reg 0x2D[3] and Reg 0x03[7:0].
0 mr_en_3G_divsel_eq RW 0 = Disables IN1 EQ Adaptation for 3G data rate
1 = Enables IN1 EQ Adaptation for 3G data rate
0x40 IN1 Index 0 Boost for Adaptation 7:6 EQ_index_0_BST0 0x00 RW Index 0 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_0_BST1 RW
3:2 EQ_index_0_BST2 RW
1:0 EQ_index_0_BST3 RW
0x41 IN1 Index 1 Boost for Adaptation 7:6 EQ_index_1_BST0 0x40 RW Index 1 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_1_BST1 RW
3:2 EQ_index_1_BST2 RW
1:0 EQ_index_1_BST3 RW
0x42 IN1 Index 2 Boost for Adaptation 7:6 EQ_index_2_BST0 0x80 RW Index 2 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_2_BST1 RW
3:2 EQ_index_2_BST2 RW
1:0 EQ_index_2_BST3 RW
0x43 IN1 Index 3 Boost for Adaptation 7:6 EQ_index_3_BST0 0x50 RW Index 3 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_3_BST1 RW
3:2 EQ_index_3_BST2 RW
1:0 EQ_index_3_BST3 RW
0x44 IN1 Index 4 Boost for Adaptation 7:6 EQ_index_4_BST0 0xC0 RW Index 4 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_4_BST1 RW
3:2 EQ_index_4_BST2 RW
1:0 EQ_index_4_BST3 RW
0x45 IN1 Index 5 Boost for Adaptation 7:6 EQ_index_5_BST0 0x90 RW Index 5 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_5_BST1 RW
3:2 EQ_index_5_BST2 RW
1:0 EQ_index_5_BST3 RW
0x46 IN1 Index 6 Boost for Adaptation 7:6 EQ_index_6_BST0 0x54 RW Index 6 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_6_BST1 RW
3:2 EQ_index_6_BST2 RW
1:0 EQ_index_6_BST3 RW
0x47 IN1 Index 7 Boost for Adaptation 7:6 EQ_index_7_BST0 0xA0 RW Index 7 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_7_BST1 RW
3:2 EQ_index_7_BST2 RW
1:0 EQ_index_7_BST3 RW
0x48 IN1 Index 8 Boost for Adaptation 7:6 EQ_index_8_BST0 0xB0 RW Index 8 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_8_BST1 RW
3:2 EQ_index_8_BST2 RW
1:0 EQ_index_8_BST3 RW
0x49 IN1 Index 9 Boost for Adaptation 7:6 EQ_index_9_BST0 0x95 RW Index 9 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_9_BST1 RW
3:2 EQ_index_9_BST2 RW
1:0 EQ_index_9_BST3 RW
0x4A IN1 Index 10 Boost for Adaptation 7:6 EQ_index_10_BST0 0x69 RW Index 10 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_10_BST1 RW
3:2 EQ_index_10_BST2 RW
1:0 EQ_index_10_BST3 RW
0x4B IN1 Index 11 Boost for Adaptation 7:6 EQ_index_11_BST0 0xD5 RW Index 11 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_11_BST1 RW
3:2 EQ_index_11_BST2 RW
1:0 EQ_index_11_BST3 RW
0x4C IN1 Index 12 Boost for Adaptation 7:6 EQ_index_12_BST0 0x99 RW Index 12 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_12_BST1 RW
3:2 EQ_index_12_BST2 RW
1:0 EQ_index_12_BST3 RW
0x4D IN1 Index 13 Boost for Adaptation 7:6 EQ_index_13_BST0 0xA5 RW Index 13 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_13_BST1 RW
3:2 EQ_index_13_BST2 RW
1:0 EQ_index_13_BST3 RW
0x4E IN1 Index 14 Boost for Adaptation 7:6 EQ_index_14_BST0 0xE6 RW Index 14 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_14_BST1 RW
3:2 EQ_index_14_BST2 RW
1:0 EQ_index_14_BST3 RW
0x4F IN1 Index 15 Boost for Adaptation 7:6 EQ_index_15_BST0 0xF9 RW Index 15 Boost
[7:6]: 2-bit control for Stage 0 of the CTLE
[5:4]: 2-bit control for Stage 1 of the CTLE.
[3:2]: 2-bit control for Stage 2 of the CTLE.
[1:0]: 2-bit control for Stage 3 of the CTLE.
5:4 EQ_index_15_BST1 RW
3:2 EQ_index_15_BST2 RW
1:0 EQ_index_15_BST3 RW
0x50 Reserved 7:0 Reserved 0x00 RW Reserved
0x51 Reserved 7:0 Reserved 0x00 RW Reserved
0x52 IN1 Active EQ Readback 7:0 eq_bst_to_ana 0x00 R IN1 CTLE boost setting readback from Active CTLE Adaptation.
0x53 Reserved 7:0 Reserved 0x00 R Reserved
0x54 Interrupt Status Register 7 cardet 0x00 R 0 = Carrier Detect from the selected input de-asserted
1 = Carrier Detect from the selected input asserted
Note: Clears when Reg 0x54 is read-back.
6 cdr_lock_int R 0 = No interrupt from CDR Lock
1 = CDR Lock Interrupt
Note: Clears when Reg 0x54 is read-back.
5 carrier_det1_int R 0 = No interrupt from IN1 Carrier Detect
1 = IN1 Carrier Detect Interrupt
Note: Clears when Reg 0x54 is read-back.
4 Reserved R Reserved
3 heo_veo_int R 0 = No interrupt from HEO/VEO
1 = HEO/VEO Threshold Reached Interrupt
Note: Clears when Reg 0x54 is read-back.
2 cdr_lock_loss_int R 0 = No interrupt from CDR Lock
1 = CDR Loss of Lock Interrupt
Note: Clears when Reg 0x54 is read-back.
1 carrier_det1_loss_int R 0 = No interrupt from IN1 Carrier Detect
1 = IN1 Carrier Detect Loss Interrupt
Note: Clears when Reg 0x54 is read-back.
0 Reserved R Reserved
0x55 Reserved 7:0 Reserved 0x02 R Reserved
0x56 Interrupt Control Register 7 Reserved 0x00 RW Reserved
6 cdr_lock_int_en RW 0 = Disable interrupt if CDR lock is achieved
1 = Enable interrupt if CDR lock is achieved
5 carrier_det1_int_en RW 0 = Disable interrupt if IN1 Carrier Detect is asserted
1 = Enable interrupt if IN1 Carrier Detect is asserted
4 Reserved RW Reserved
3 heo_veo_int_en RW 0 = Disable interrupt if HEO/VEO threshold is reached
1 = Enable interrupt if HEO/VEO threshold is reached
2 cdr_lock_loss_int_en RW 0 = Disable interrupt if CDR loses lock
1 = Enable interrupt if CDR loses lock
1 carrier_det1_loss_int_en RW 0 = Disable interrupt if there is loss of signal (LOS) on IN1
1 = Enable interrupt if there is loss of signal (LOS) on IN1
0 Reserved RW Reserved
0x60 Reserved 7:0 Reserved 0x26 RW Reserved
0x61 Reserved 7:0 Reserved 0x31 RW Reserved
0x62 Reserved 7:0 Reserved 0x70 RW Reserved
0x63 Reserved 7:0 Reserved 0x3D RW Reserved
0x64 Reserved 7:0 Reserved 0xFF RW Reserved
0x65 Reserved 7:0 Reserved 0x00 RW Reserved
0x66 Reserved 7:0 Reserved 0x00 RW Reserved
0x67 Reserved 7:0 Reserved 0x00 RW Reserved
0x68 Reserved 7:0 Reserved 0x00 RW Reserved
0x69 HEO_VEO Lock Monitor 7:4 Reserved 0x0A RW Reserved
3:0 hv_lckmon_cnt_ms RW While monitoring lock, these bits set the amount of interval times to monitor HEO or VEO lock. Each interval is 6.5 ms. Therefore, by default, Reg 0x69[3:0] = 1010'b causes HEO_VEO lock monitor to occur once every 65 ms.
0x6A HEO and VEO Lock Threshold 7:4 veo_lck_thrsh 0x44 RW HEO/VEO lock thresholds. Lock will not be declared until HEO ≥ (heo_lck_thrsh x 4) and VEO ≥ (veo_lck_thrsh x 4).
3:0 heo_lck_thrsh RW
0x6B Reserved 7:0 Reserved 0x40 RW Reserved
0x6C Reserved 7:0 Reserved 0x00 RW Reserved
0x6D Reserved 7:0 Reserved 0x00 RW Reserved
0x6E Reserved 7:0 Reserved 0x00 RW Reserved
0x6F Reserved 7:0 Reserved 0x00 RW Reserved
0x70 Reserved 7:0 Reserved 0x03 RW Reserved
0x71 Reserved 7:0 Reserved 0x20 R Reserved
0x72 Reserved 7:0 Reserved 0x00 RW Reserved
0x73 Reserved 7:0 Reserved 0x00 RW Reserved
0x74 Reserved 7:0 Reserved 0x00 RW Reserved
0x75 Reserved 7:0 Reserved 0x00 RW Reserved
0x77 Reserved 7:0 Reserved 0x00 RW Reserved
0x80 Reserved 7:0 Reserved 0x50 RW Reserved
0x81 Reserved 7:0 Reserved 0x00 RW Reserved
0x82 Reserved 7:0 Reserved 0x80 RW Reserved
0x83 Reserved 7:0 Reserved 0x70 RW Reserved
0x84 Reserved 7:0 Reserved 0x04 RW Reserved
0x85 Reserved 7:0 Reserved 0x00 RW Reserved
0x87 Reserved 7:0 Reserved 0x00 RW Reserved
0x90 Reserved 7:0 Reserved 0xA5 RW Reserved
0x91 Reserved 7:0 Reserved 0x23 RW Reserved
0x92 Reserved 7:0 Reserved 0x2C RW Reserved
0x93 Reserved 7:0 Reserved 0x32 RW Reserved
0x94 Reserved 7:0 Reserved 0x37 RW Reserved
0x95 Reserved 7:0 Reserved 0x3E RW Reserved
0x98 Reserved 7:0 Reserved 0x3F RW Reserved
0x99 Reserved 7:0 Reserved 0x04 RW Reserved
0x9A Reserved 7:0 Reserved 0x04 RW Reserved
0x9B Reserved 7:0 Reserved 0x04 RW Reserved
0x9C Reserved 7:0 Reserved 0x06 RW Reserved
0x9D Reserved 7:0 Reserved 0x04 RW Reserved
0x9E Reserved 7:0 Reserved 0x04 RW Reserved
0xA0 SMPTE Data Rate Lock Enable 7:5 Reserved 0x1F RW Reserved
4 dvb_enable RW 0 = Disable CDR Lock to 270 Mbps
1 = Enable CDR Lock to 270 Mbps
3 hd_enable RW 0 = Disable CDR Lock to 1.485/1.4835 Gbps
1 = Enable CDR Lock to 1.485/1.4835 Gbps
2 3G_enable RW 0 = Disable CDR Lock to 2.97/2.967 Gbps
1 = Enable CDR Lock to 2.97/2.967 Gbps
1 6G_enable RW 0 = Disable CDR Lock to 5.94/5.934 Gbps
1 = Enable CDR Lock to 5.94/5.934 Gbps
0 12G_enable RW 0 = Disable CDR Lock to 11.88/11.868 Gbps
1 = Enable CDR Lock to 11.88/11.868 Gbps