SNOSDC1 June 2024 LMH1229
ADVANCE INFORMATION
Each SPI transaction to a single device is 17 bits long and is framed by CS_N when asserted low. The PICO input is ignored, and the POCI output is floated whenever CS_N is deasserted (high).
The bits are shifted in left-to-right. The first bit is R/ W, which is 1'b for read and 0'b for write. Bits A7-A0 are the 8-bit register address, and bits D7-D0 are the 8-bit read or write data. The previous SPI command, address, and data are shifted out on POCI as the current command, address, and data are shifted in on PICO. In all SPI transactions, the POCI output signal is enabled asynchronously when CS_N asserts low. The contents of a single PICO or POCI transaction frame are shown in Table 6-11.
R/ W | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |