SNOSDC1 June 2024 LMH1229
ADVANCE INFORMATION
Legend | |||
---|---|---|---|
High Speed Signals | Serial Control Interface (SPI or SMBus) Pins | Reserved Pins | |
Control Pins | Power (2.5 V) | LDO Output (1.8 V) | GND |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | LMH1229 NO. | LMH1239 NO. | ||
HIGH SPEED DIFFERENTIAL I/Os | ||||
SDI_IN+ | 1 | 1 | I, Analog | Single-ended complementary inputs with on-chip 75Ω termination at
SDI_IN+ and SDI_IN-. Either SDI_IN+ or SDI_IN- can be used as the 75Ω input port of
the adaptive cable equalizer for SMPTE video applications. SDI_IN± include
integrated return loss networks designed to meet the SMPTE input and output return
loss requirements. Connect either SDI_IN+ or SDI_IN- to a BNC through a 4.7µF AC coupling capacitor. AC terminate the unused polarity (SDI_IN- or SDI_IN+, respectively) with external 4.7µF and 75Ω to GND. |
SDI_IN- | 2 | 2 | I, Analog | |
SDI_IN1+ | N/A | 29 | I, Analog | Redundant single-ended complementary inputs with on-chip 75Ω
termination at SDI_IN1+ and SDI_IN1-. Either SDI_IN1+ or SDI_IN1- can be used as a
secondary 75Ω input port of the adaptive cable equalizer for SMPTE video
applications. SDI_IN1± include integrated return loss networks designed to meet the
SMPTE input and output return loss requirements. Connect either SDI_IN1+ or SDI_IN1- to a BNC through a 4.7µF AC coupling capacitor. AC terminate the unused polarity (SDI_IN- or SDI_IN+, respectively) with external 4.7µF and 75Ω to GND. |
SDI_IN1- | N/A | 30 | I, Analog | |
SDI_OUT+ | 8 | 8 | O, Analog | Single-ended complementary loop-through cable
driver outputs with on-chip 75Ω termination at SDI_OUT+ and SDI_OUT-. SDI_OUT±
include integrated return loss networks designed to meet the SMPTE output return
loss requirements. Connect either SDI_OUT+ or SDI_OUT- to a BNC through a 4.7µF AC coupling capacitor. AC terminate the unused polarity (SDI_IN- or SDI_IN+, respectively) with external 4.7µF and 75Ω to GND. Note that Cable Fault Detection is only available when using the SDI_OUT+ polarity. |
SDI_OUT- | 7 | 7 | O, Analog | |
OUT0+ | 23 | 23 | O, Analog | Differential complementary outputs with 100Ω internal termination. Requires external 4.7µF AC coupling capacitors. Output driver OUT0± can be disabled under user control. |
OUT0- | 22 | 22 | O, Analog | |
OUT1+ | 19 | 19 | O, Analog | Differential complementary outputs with 100Ω internal termination. Requires external 4.7µF AC coupling capacitors. Output driver OUT1± can be disabled under user control. |
OUT1- | 18 | 18 | O, Analog | |
CONTROL PINS | ||||
LOOP_BW_SEL | 4 | 4 | I, 4-Level | LOOP_BW_SEL enables 4-level CDR loop bandwidth control.
Additional CDR loop bandwidth settings are available by register override. |
IN_MUX_SEL | N/A | 10 | I, 4-Level | LMH1239 Only: IN_MUX_SEL selects between SDI_IN or SDI_IN1. This
pin setting can be overridden by register control. See Table 6-3 for details. |
OUT_MUX_SEL | 5 | 5 | I, 4-Level | OUT_MUX_SEL controls OUT0± and OUT1± enable behavior. This pin
setting can be overridden using register control. See Table 6-3 for details. |
VOD_DE | 9 | 9 | I, 4-Level | VOD_DE selects the driver output amplitude and de-emphasis level
for both OUT0± and OUT1±. This pin setting can be overridden by register control. See Table 6-8 for details. |
MODE_SEL | 12 | 12 | I, 4-Level | MODE_SEL enables SPI or SMBus serial control interface. See Table 6-9 for details. |
SDI_OUT_SEL | 14 | 14 | I, LVCMOS | SDI_OUT_SEL enables the use of the 75Ω output driver at
SDI_OUT±. SDI_OUT_SEL is internally pulled high. The SDI_OUT± is turned off by
default. See Table 6-4 for details. |
LF+ | 15 | 15 | I, Analog | Optional 470nF external loop filter capacitor connected between LF+ and LF- for reduced CDR loop bandwidth settings. If reduced CDR loop bandwidth is not required, these pins must be left floating (no connect). |
LF- | 16 | 16 | I, Analog | |
OUT_CTRL | 17 | 17 | I, 4-Level | OUT_CTRL selects the signal flow from the SDI input (either
SDI_IN± or SDI_IN1±) to OUT0± and OUT1±. It selects reclocked data, reclocked data
and clock, or bypassed reclocker data (equalized data to output driver). This pin
setting can be overridden by register control. See Table 6-6 for details. |
SDI_VOD | 24 | 24 | I, 4-Level | SDI_VOD selects one of four output amplitudes for the cable
drivers at SDI_IO± and SDI_OUT±. See Table 6-7 for details. |
LOCK_N | 27 | 25 | O, LVCMOS, OD | LOCK_N is the reclocker lock indicator for the selected input. LOCK_N is pulled LOW when the reclocker has acquired locking condition. LOCK_N is an open drain output, 3.3V tolerant, and requires an external 2kΩ to 5kΩ pullup resistor to logic supply. LOCK_N pin can be re-configured to indicate CD_N (Carrier Detect), Cable Fault Detect (CFD_N), or INT_N (Interrupt) for the selected SDI input through register programming. |
ENABLE | 32 | 32 | I, LVCMOS | ENABLE controls device operation. A logic-low on ENABLE configures device in power down state. A logic-high on ENABLE configures the device in normal operation. ENABLE has an internal weak pull up. |
SERIAL CONTROL INTERFACE | ||||
CS_N_ADDR0 | 11 | 11 | SPI Mode: I, LVCMOS SMBus Mode: Strap, 4-Level |
SPI Mode (MODE_SEL = F): CS_N CS_N is the Chip Select. When CS_N is at logic Low, the pin enables SPI access to the LMH12x9 peripheral device. CS_N is a LVCMOS input pulled high by default. SMBus Mode (MODE_SEL = L): ADDR0 ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus addresses. ADDR[1:0] are 4-level straps and are read into the device at power up. See Table 6-10 for details. |
POCI_ADDR1 | 28 | 26 | SPI Mode: O, LVCMOS SMBus Mode: Strap, 4-Level |
SPI Mode (MODE_SEL = F): POCI POCI "Peripheral Output Controller Input" is the SPI control serial data output from the LMH12x9 peripheral device. POCI is a LVCMOS output referenced to VIN. SMBus Mode (MODE_SEL = L): ADDR1 ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus addresses. ADDR[1:0] are 4-level straps and are read into the device at power up. See Table 6-10 for details. |
PICO_SDA | 13 | 13 | SPI Mode: I, LVCMOS SMBus Mode: IO, LVCMOS, OD |
SPI Mode (MODE_SEL = F): PICO PICO "Peripheral Input Controller Output" is used as the SPI control serial data input to the LMH12x9 peripheral device. PICO is LVCMOS input referenced to VIN SMBus Mode (MODE_SEL = L): SDA SDA is the SMBus bi-directional open drain SDA data line to or from the LMH12x9 target device. SDA is an open drain IO and 3.3V tolerant. SDA requires an external 2kΩ to 5kΩ pullup resistor to the SMBus termination voltage. |
SCK_SCL | 29 | 27 | SPI Mode: I, LVCMOS SMBus Mode: I, LVCMOS, OD |
SPI Mode (MODE_SEL = F): SCK SCK is the SPI serial input clock to the LMH12x9 peripheral device. SCK is LVCMOS referenced to VIN. SMBus Mode (MODE_SEL = L): SCL SCL is the SMBus input clock to the LMH12x9 target device when SMBus is enabled. The pin is driven by a LVCMOS open drain driver from the SMBus controller and is 3.3V tolerant. SCL requires an external 2kΩ to 5kΩ pullup resistor to the SMBus termination voltage. |
RESERVED | ||||
RSV1 | 10 | N/A | N/A | Reserved pins. Do not connect. |
RSV2 | 25 | N/A | ||
RSV3 | 26 | N/A | ||
POWER | ||||
VSS | 3, 6, 20 | 3, 6, 20 | I, Ground | Ground reference. |
VIN | 30, 21 | 28, 21 | I, Power | VIN should be connected to the same external 2.5V ± 5% power supply. TI recommends to place decoupling capacitors as close as possible to both VIN pins. |
VDD_LDO | 31 | 31 | O, Power | VDD_LDO is the output of the internal 1.8V LDO regulator. VDD_LDO output requires an external 1µF and 0.1µF bypass capacitor to VSS. The internal LDO is designed to power internal circuitry only. |
EP | I, Ground | EP is the exposed pad at the bottom of the QFN package. The exposed pad must be connected to the ground plane through a 3x3 via array. |